Pulse Per Second Input; Cryptographic Functions; Cpacf Functions (Fc 3863); Crypto Express5S Feature (Fc 0890) - IBM z13s Technical Manual

For more information about STP configuration, see these books:
Server Time Protocol Planning Guide, SG24-7280
Server Time Protocol Implementation Guide, SG24-7281
Server Time Protocol Recovery Guide, SG24-7380

4.9.3 Pulse per second input

A pulse per second (PPS) signal can be received from an External Time Source (ETS)
device. One PPS port is available on each of the two oscillator cards, which are installed on a
small backplane mounted in the rear of the z13s frame, with connection to all the CEC
drawers. These cards provide redundancy for continued operation and concurrent
maintenance when a single oscillator card fails. Each oscillator card has a Bayonet
Neill-Concelman (BNC) connector for PPS connection support, attaching to two different
ETSs. Two PPS connections from two different ETSs are preferable for redundancy.
The time accuracy of an STP-only CTN is improved by adding an ETS device with the PPS
output signal. STP tracks the highly stable and accurate PPS signal from ETSs. It maintains
accuracy of 10 µs as measured at the PPS input of the z13s server. If STP uses an NTP
server without PPS, a time accuracy of 100 ms to the ETS is maintained. ETSs with PPS
output are available from various vendors that offer network timing solutions.

4.10 Cryptographic functions

Cryptographic functions are provided by the CP Assist for Cryptographic Function (CPACF)
and the PCI Express cryptographic adapters. z13s servers support the Crypto Express5S
feature.

4.10.1 CPACF functions (FC 3863)

FC 3863 is required to enable CPACF functions. FC 3863 is subject to export regulations.

4.10.2 Crypto Express5S feature (FC 0890)

Crypto Express5S is a new feature on z13 and z13s servers. On the initial configuration, a
minimum of two features are installed. The number of features increases one at a time up to a
maximum of 16 features. Each Crypto Express5S feature holds one PCI Express
cryptographic adapter. Each adapter can be configured by the installation as a Secure IBM
Common Cryptographic Architecture (CCA) coprocessor, as a Secure IBM Enterprise Public
Key Cryptography Standards (PKCS) #11 (EP11) coprocessor, or as an accelerator.
Each Crypto Express5S feature occupies one I/O slot in the PCIe I/O drawer, and has no
CHPID assigned. However, it has one PCHID.

4.11 Integrated firmware processor

The integrated firmware processor (IFP) was initially introduced with the zEC12 and zBC12
servers. The IFP is dedicated for managing a new generation of PCIe features. These new
features are installed exclusively in the PCIe I/O drawer:
zEDC Express
Chapter 4. Central processor complex I/O system structure
183