Reserved Processors; Integrated Firmware Processor; Processor Unit Assignment - IBM z13s Technical Manual

3.5.7 Reserved processors

Reserved processors
Reserved processors are like spare logical processors, and can be shared or dedicated.
Reserved CPs can be defined to an LPAR dynamically to allow for nondisruptive image
upgrades.
Reserved processors can be dynamically configured online by an operating system that
supports this function if enough unassigned PUs are available to satisfy this request. The
PR/SM rules that govern logical processor activation remain unchanged.
By using reserved processors, you can define more logical processors than the number of
available CPs, IFLs, ICFs, and zIIPs in the configuration to an LPAR. This definition makes it
possible to configure online, nondisruptively, more logical processors after more CPs, IFLs,
ICFs, and zIIPs are made available concurrently. They can be made available with one of the
Capacity on Demand options.
The maximum number of reserved processors that can be defined to an LPAR depends on
the number of logical processors that are already defined. The maximum number of logical
processors plus reserved processors is 20. If the operating system in the LPAR supports the
logical processor add function, reserved processors are no longer needed.
Do not define more active and reserved processors than the operating system for the LPAR
can support. For more information about logical processors and reserved processors and
their definitions, see 3.7, "Logical partitioning" on page 116.

3.5.8 Integrated firmware processor

An IFP is allocated from the pool of PUs. This is available for the whole system. Unlike other
characterized PUs, the IFP is standard and not defined by the client. It is a single PU
dedicated solely to supporting the
features (10GbE Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE)
Express and zEnterprise Data Compression (zEDC) Express) and is initialized at POR. The
IFP supports Resource Group LIC to provide native PCIe I/O feature management and
virtualization functions. For more information, see Appendix G, "Native Peripheral Component
Interconnect Express" on page 521.

3.5.9 Processor unit assignment

The processor unit assignment of characterized PUs is done at POR time, when the system
is initialized. The initial assignment rules keep PUs of the same characterization type grouped
as much as possible in relation to PU chips and CPC drawer boundaries to optimize shared
cache usage.
The PU assignment is based on CPC drawer plug ordering. The CPC drawers are populated
from the bottom upward. This process defines the low-order and the high-order CPC drawers:
CPC drawer 1: Plug order 1 (low-order CPC drawer)
CPC drawer 0: Plug order 2 (high-order CPC drawer)
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IBM z13s Technical Guide
are defined by the PR/SM to allow for a nondisruptive capacity upgrade.
native
Peripheral Component Interconnect Express (PCIe)