Translation Lookaside Buffer; Instruction Fetching, Decoding, And Grouping; Extended Translation Facility - IBM z13s Technical Manual

3.4.11 Translation lookaside buffer

The TLB in the instruction and data L1 caches use a secondary TLB to enhance
performance. In addition, a translator unit is added to translate misses in the secondary TLB.
The size of the TLB is kept as small as possible because of its short access time
requirements and hardware space limitations. Because memory sizes have recently
increased significantly as a result of the introduction of 64-bit addressing, a smaller working
set is represented by the TLB. To increase the working set representation in the TLB without
enlarging the TLB, large (1 MB) page and giant page (2 GB) support is available and can be
used when appropriate. For more information, see "Large page support" on page 114.
With the enhanced DAT-2 (EDAT-2) improvements, the z Systems introduce architecture
enhancements to allow support for 2 GB page frames.

3.4.12 Instruction fetching, decoding, and grouping

The superscalar design of the microprocessor allows for the decoding of up to six instructions
per cycle and the execution of up to 10 instructions per cycle. Both execution and storage
accesses for instruction and operand fetching can occur out of sequence.
Instruction fetching
Instruction fetching normally tries to get as far ahead of instruction decoding and execution as
possible because of the relatively large instruction buffers available. In the microprocessor,
smaller instruction buffers are used. The operation code is fetched from the I-cache and put in
instruction buffers that hold prefetched data that is awaiting decoding.
Instruction decoding
The processor can decode up to six instructions per cycle. The result of the decoding process
is queued and later used to form a group.
Instruction grouping
From the instruction queue, up to 10 instructions can be completed on every cycle. A
complete description of the rules is beyond the scope of this book.
The compilers and JVMs are responsible for selecting instructions that best fit with the
superscalar microprocessor. They abide by the rules to create code that best uses the
superscalar implementation. All the z Systems compilers and the JVMs are constantly
updated to benefit from new instructions and advances in microprocessor designs.

3.4.13 Extended Translation Facility

Instructions have been added to the z/Architecture instruction set in support of the Extended
Translation Facility. They are used in data conversion operations for Unicode data, causing
applications that are enabled for Unicode or globalization to be more efficient. These
data-encoding formats are used in web services, grid, and on-demand environments where
XML and SOAP technologies are used. The High Level Assembler supports Extended
Translation Facility instructions.
Chapter 3. Central processor complex system design
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