Simultaneous Multi-Threading - IBM 9123710 - eServer OpenPower 710 Introduction Manual

Figure 2-2 POWER5 system structure
Because of the higher transistor density of the POWER5 0.13-
to move the memory controller on the processor chip and eliminate a chip previously needed
for the memory controller function. These changes in the POWER5 processor also have the
significant side benefits of reducing latency to the L3 cache and main memory, as well as
reducing the number of chips necessary to build a system.

2.1.1 Simultaneous multi-threading

As a requirement for performance improvements at the application level, simultaneous
multi-threading functionality is embedded in the POWER5 chip technology. Applications
developed to use process-level parallelism (multi-tasking) and thread-level parallelism
(multi-threads) can shorten their overall execution time. Simultaneous multi-threading is the
next stage of processor saturation for throughput-oriented applications to introduce the
method of instruction-level parallelism to support multiple pipelines to the processor.
The simultaneous multi-threading mode maximizes the usage of the execution units. In the
POWER5 chip, more rename registers have been introduced (for floating-point operation,
rename registers increased to 120), which are essential for out-of-order execution, and then
vital for simultaneous multi-threading.
If simultaneous multi-threading is activated:
More instructions can be executed at the same time.
The operating system views twice the number of physical processors installed in the
system.
Provides support in mixed environments:
– Capped and uncapped partitions
– Virtual partitions
– Dedicated partitions
– Single partition systems
Note: Simultaneous multi-threading is supported on POWER5 processor-based systems
running Linux operating system-based systems at an appropriate level.
POWER5 POWER5
Processor Processor Processor Processor
L3 L3 L2 L2
cache cache cache cache
Fabric Fabric
controller controller
Memory Memory
controller controller
Memory Memory
Processor Processor Processor Processor
L2 L2
cache cache
Fabric Fabric
controller controller
Memory Memory
controller controller
Memory Memory
m technology, it was possible
µ
Chapter 2. Architecture and technical overview
L3 L3
cache cache
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