Memory Subsystem Topology; Cpc Drawer Memory Topology - IBM z13s Technical Manual

Note: The required granularity for all main storage fields of an LPAR for which an origin
has been specified (for example, initial main storage amount, reserved main storage
amount, and main storage origin) is fixed at 2 GB. This configuration helps to simplify
customer management of absolute storage regarding 2 GB large page support for these
partitions. In support of 2 GB large pages, all logical partition origin MBs and limit MBs
must be on a 2 GB boundary.

2.4.1 Memory subsystem topology

The z13s memory subsystem uses high speed, differential-ended communications memory
channels to link a host memory to the main memory storage devices.
Figure 2-17 shows an overview of the CPC drawer memory topology of a z13s server.
Figure 2-17 CPC drawer memory topology
Each CPC drawer has up to 20 DIMMs. DIMMs are connected to each PU chip through the
MCUs. Each PU chip has one MCU, which uses five channels, one for each DIMM and one
for RAIM implementation, in a 4 +1 design.
Each DIMM can be 16 GB, 32 GB, 64 GB, or 128 GB. DIMM sizes cannot be mixed in the
same CPC drawer, but a two CPC drawer Model N20 can have different (but not mixed) DIMM
sizes in each drawer.
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IBM z13s Technical Guide
MCU 1 MCU2
MD06 MD11
MD07 MD12
MD08 MD13
MD09 MD14
MD10 MD15
MCU MCU
PU1 PU2
SC1
MCU 3
MD16
Channel 0
MD17
Channel 1
MD18
Channel 2
MD19
Channel 3
MD20
Channel 4
MCU
PU3
SC0
MCU 4
MD21
Channel 0
MD22
Channel 1
MD23
Channel 2
MD24
Channel 3
MD25
Channel 4
MCU
PU4
Depopulated SCM
and DIMM locations
not shown.