Processor Unit Design; Point-To-Point Topology Z13S Two Cpc Drawers Communication - IBM z13s Technical Manual

Figure 3-5 shows a simplified topology of a z13s two CPC drawer system.
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Figure 3-5 Point-to-point topology z13s two CPC drawers communication
Inter-CPC drawer communication takes place at the L4 cache level, which is implemented on
SC SCMs in each node. The SC function regulates coherent node-to-node traffic.

3.4 Processor unit design

Processor cycle time is especially important for processor-intensive applications. Current
systems design is driven by processor cycle time, although improved cycle time does not
automatically mean that the performance characteristics of the system improve. The
System z10 BC introduced a dramatic PU cycle time improvement. Its succeeding
generations, the z114 and the zBC12, reduced the cycle time even further, reaching 0.263 ns
(3.8 GHz) and 0.238 ns (4.2 GHz).
z13s servers have a cycle time of 0.232 ns (4.3 GHz), and an improved design that allows the
increased number of processors that share larger caches to have quick access times and
improved capacity and performance. Although the cycle time of the z13s processor has only
slightly decreased compared to zBC12 (2.4%), the processor performance was increased
much more through improved processor design, such as redesigned pipeline and out-of-order
execution, branch prediction, time of access to high-speed buffers (caches redesign), and the
relative nest intensity (RNI). For more information about RNI, see 12.4, "Relative nest
intensity" on page 441.
The z13s processor unit core is a superscalar, OOO, SMT processor with 10 execution units
(compared to six for zBC12). For instructions that are not directly run by the hardware, some
are run by millicode, and others are split into multiple operations.
The z13s system introduces architectural extensions with instructions that are designed to
allow reduced processor quiesce effects, reduced cache misses, reduced pipeline disruption,
and increased parallelism with instructions that process several operands in a single
instruction (SIMD). The new z13s architecture includes the following features:
SMT
SIMD instructions set
Improved OOO core execution
Improvements in branch prediction and handling
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