Processor Unit (Core) - IBM z13s Technical Manual

2.3.3 Processor unit (core)

Each processor unit, or core, is a superscalar and out-of-order processor that has 10
execution units and two load/store units, which are divided into two symmetric pipelines as
follows:
Four fixed-point units (FXUs) (integer)
Two load/store units (LSUs)
Two binary floating-point units (BFUs)
Two binary coded decimal floating-point units (DFUs)
Two vector floating point units (vector execution units (VXUs))
Up to six instructions can be decoded per cycle, and up to 10 instructions/operations can be
initiated to run per clock cycle. The running of the instructions can occur out of program order,
and memory address generation and memory accesses can also occur out of program order.
Each core has special circuitry to display execution and memory accesses in order to the
software. Not all instructions are directly run by the hardware, which is the case for several
complex instructions. Some are run by millicode, and some are broken into multiple
operations that are then run by the hardware.
Each core has the following functional areas, which are also shown in Figure 2-14 on
page 50:
Instruction sequence unit (ISU): This unit enables the out-of-order (OOO) pipeline. It
tracks register names, OOO instruction dependency, and handling of instruction resource
dispatch.
This unit is also central to performance measurement through a function called
instrumentation
Instruction fetch and branch (IFB) (prediction) and instruction cache and merge (ICM):
These two subunits (IFB and ICM) contain the instruction cache, branch prediction logic,
instruction fetching controls, and buffers. The relative size of these subunits is the result of
the elaborate branch prediction design, which is described in 3.4.4, "Superscalar
processor" on page 95.
Instruction decode unit (IDU): The IDU is fed from the IFB buffers, and is responsible for
the parsing and decoding of all z/Architecture operation codes.
Load/store unit (LSU): The LSU contains the data cache. It is responsible for handling all
types of operand accesses of all lengths, modes, and formats that are defined in the
z/Architecture.
Translation unit (XU): The XU has a large translation look aside buffer (TLB) and the
dynamic address translation (DAT) function that handles the dynamic translation of logical
to physical addresses.
Core pervasive unit - PC: Used for instrumentation and error collection.
Vector and floating point units:
– Fixed-point unit (FXU): The FXU handles fixed-point arithmetic.
– Binary floating-point unit (BFU): The BFU handles all binary and hexadecimal
floating-point and fixed-point multiplication operations.
– Decimal floating-point unit (DFU): The DFU runs both floating-point and decimal
fixed-point operations and fixed-point division operations.
– Vector execution unit (VXU)
.
Chapter 2. Central processor complex hardware components
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