Cpc Drawer Design; Cache Levels And Memory Structure; Z13S Cache Levels And Memory Hierarchy - IBM z13s Technical Manual

3.3 CPC drawer design

A z13s system can have up to two CPC drawers in a full configuration, up to 20 PUs can be
characterized, and up to 4 TB of customer usable memory capacity can be ordered. Each
CPC drawer is physically divided into two nodes to improve the processor and memory affinity
and availability. The CPC drawer topology is shown in Figure 3-5 on page 88.
Memory has up to four memory controllers that use 5-channel redundant array of
independent memory (RAIM) protection, with dual inline memory modules (DIMM) bus cyclic
redundancy check (CRC) error retry. The 4-level cache hierarchy is implemented with
eDRAM (embedded) caches. Until recently, eDRAM was considered to be too slow for this
use. However, a breakthrough in technology by IBM has removed that limitation. In addition,
eDRAM offers higher density, less power utilization, fewer soft errors, and better performance.
z13s servers use CMOS 14S0 Silicon-On-Insulator (SOI) 22 nm chip technology, with
advanced low latency pipeline design, creating high-speed yet power-efficient circuit designs.
The PU SCM has a dense packaging, but due to lower cycle frequency can be air cooled.

3.3.1 Cache levels and memory structure

The z13s memory subsystem focuses on keeping data "closer" to the PU core. With the
current processor configuration, all cache levels have increased, and the second-level private
cache (L2) and the total node-level shared cache (L4 including NIC directory) in a central
processor complex (CPC) drawer have doubled in size.
Figure 3-1 shows the z13s cache levels and memory hierarchy.
Main
Storage
Level 4
Level 3
Level 2
Level 1
Figure 3-1 z13s cache levels and memory hierarchy
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IBM z13s Technical Guide
2 TB per processor drawer / spread over 20 DIMMs / 4.0 TB per CEC
DRAM
480 MB + 224MB
NIC directory
eDRAM
64 MB
eDRAM
2 MB / 2 MB
96 KB I-cache
128 KB D-cache
DIMMs
One cache (SC chip)
per node (two nodes
per processor
drawers)
SC Chip
One per PU Chip
(shared by 6 or 7
cores)
1 per core, 6 or 7 per
SRAM
PU Chip
SRAM
PU Chip
up to four nodes
up to 8
(PU chips)