Simultaneous Multi-Threading - IBM p5 590 System Handbook

2.2.1 Simultaneous multi-threading

As a permanent requirement for performance improvements at the application
level, simultaneous multi-threading functionality is embedded in the POWER5
chip technology. Developers are familiar with process-level parallelism
(multi-tasking) and thread-level parallelism (multi-threads). Simultaneous
multi-threading is the next stage of processor for achieving higher processor
utilization for throughput-oriented applications to introduce the method of
instruction group-level parallelism to support multiple pipelines to the processor.
The instruction groups are chosen from different hardware threads belonging to a
single OS image.
Simultaneous multi-threading is activated by default when an OS that supports it
is loaded. On a 2-way POWER5 processor-based system, the operating system
discovers the available processors as a 4-way system. To achieve a higher
performance level, simultaneous multi-threading is also applicable in
Micro-Partitioning, capped or uncapped, and dedicated partition environments.
Simultaneous multi-threading is supported on POWER5 processor-based
systems running AIX 5L Version 5.3 or Linux OS-based systems at the correct
kernel level. AIX 5L provides the smtctl command that turns simultaneous
multi-threading on and off without subsequent reboot. For Linux, an additional
boot option must be set to activate simultaneous multi-threading after a reboot.
The simultaneous multi-threading mode increases the usage of the execution
units. In the POWER5 chip, more rename registers have been introduced (both
Floating-Point registers (FPR) and general-purpose registers (GPR) are
increased to 120), that are essential for out-of-order execution and vital for the
simultaneous multi-threading.
Enhanced simultaneous multi-threading features
To improve simultaneous multi-threading performance for various workload
mixes and provide robust quality of service, POWER5 provides two features:
Dynamic resource balancing
The objective of dynamic resource balancing is to ensure that the two threads
executing on the same processor flow smoothly through the system.
Depending on the situation, the POWER5 processor resource balancing logic
has a different thread throttling mechanism.
Adjustable thread priority
Adjustable thread priority lets software determine when one thread should
have a greater (or lesser) share of execution resources.
The POWER5 processor supports eight software-controlled priority levels for
each thread.
IBM Eserver p5 590 and 595 System Handbook
20