Superscalar Processor; Compression And Cryptography Accelerators On A Chip - IBM z13s Technical Manual

3.4.4 Superscalar processor

scalar processor
A
that only a single instruction is run at a time. A
(parallel) execution of instructions by adding more resources to the microprocessor in multiple
pipelines, each working on its own set of instructions to create parallelism.
A superscalar processor is based on a multi-issue architecture. However, when multiple
instructions can be run during each cycle, the level of complexity is increased because an
operation in one pipeline stage might depend on data in another pipeline stage. Therefore, a
superscalar design demands careful consideration of which instruction sequences can
successfully operate in a long pipeline environment.
On z13s servers, up to six instructions can be decoded per cycle and up to 10 instructions or
operations can be in execution per cycle. Execution can occur out of (program) order. These
improvements also make the simultaneous execution of two threads in the same processor
possible.
Many challenges exist in creating an efficient superscalar processor. The superscalar design
of the PU has made significant strides in avoiding address generation interlock (AGI)
situations. Instructions that require information from memory locations can suffer multi-cycle
delays while getting the needed memory content. Because high-frequency processors wait
"faster" (spend processor cycles more quickly while idle), the cost of getting the information
might become prohibitive.

3.4.5 Compression and cryptography accelerators on a chip

This section describes the compression and cryptography features.
Coprocessor units
Each core in the chip has one coprocessor (COP) unit for compression and cryptography. The
compression engine uses static dictionary compression and expansion. The compression
dictionary uses the L1-cache (instruction cache).
The cryptography engine is used for CPACF, which offers a set of symmetric cryptographic
functions for encrypting and decrypting of clear key operations.
These are some of the characteristics of the z13s coprocessors:
Each core has an independent compression and cryptographic engine.
COP has been redesigned from scratch to support SMT operation and to increase
throughput.
It is available to any processor type.
The owning processor is busy when its coprocessor is busy.
is a processor that is based on a single-issue architecture, which means
Chapter 3. Central processor complex system design
superscalar processor
allows concurrent
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