High-Speed Counter Definition, High-Speed Counter; Understanding The High-Speed Counter Instructions - Siemens SIMATIC S7-200 System Manual

High-Speed Counter Definition, High-Speed Counter

L
A
EN
D
HSC
MODE
EN
N
S
HDEF HSC, MODE
T
L
HSC
222 224
221
Inputs/Outputs
HSC Constant
MODE Constant
N Constant

Understanding the High-Speed Counter Instructions

High-speed counters count high-speed events that cannot be controlled at CPU
scan rates, and can be configured for up to twelve different modes of operation.
The counter modes are listed in Table 9-5. The maximum counting frequency of a
high-speed counter is dependent upon your CPU type. See Appendix A for more
information about your CPU.
Each counter has dedicated inputs for clocks, direction control, reset, and start,
where these functions are supported. For the two-phase counters, both clocks may
run at their maximum rates. In quadrature modes, an option is provided to select
one times (1x) or four times (4x) the maximum counting rates. All counters run at
maximum rates without interfering with one another.
S7-200 Programmable Controller System Manual
A5E00066097-02
The High-Speed Counter Definition instruction assigns
a MODE to the referenced high-speed counter (HSC).
HDEF
ENO
See Table 9-5 on page 9-33.
The High-Speed Counter instruction, when executed,
configures and controls the operational mode of the
high-speed counter, based on the state of the HSC
special memory bits. The parameter N specifies the
HSC
high-speed counter number.
ENO
CPU 221 and CPU 222 do not support HSC1 and HSC2.
Only one HDEF box may be used per counter.
HDEF: Error conditions that set ENO = 0:
SM4.3 (run-time), 0003 (input point conflict), 0004 (illegal
N
instruction in interrupt), 000A (HSC redefinition)
HSC: Error conditions that set ENO = 0:
226
SM4.3 (run-time), 0001 (HSC before HDEF), 0005
(simultaneous HSC/PLS)
Operands
SIMATIC Instructions
Data Types
BYTE
BYTE
WORD
9-27