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Figure 4 provides the output timing diagram for the 603.
SYSCLK
12
ALL OUTPUTS
(Except TS, ABB,
DBB, ARTRY
TS
ABB, DBB
ARTRY
1.4.3 JTAG AC Timing Specifications
Table 9 provides the JTAG AC timing specifications as defined in Figure 5 through Figure 8.
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C
Num
TCK frequency of operation
1
TCK cycle time
2
TCK clock pulse width measured at 1.4 V
3
TCK rise and fall times
4
TRST setup time to TCK rising edge
5
TRST assert time
6
Boundary-scan input data setup time
603 Hardware Specifications
VM
14
15
16
13
VM = Midpoint Voltage (1.4 V)
Figure 4. Output Timing Diagram
= 50 pF, 0 ≤ T
L
Characteristic
VM
13
15
16
17
21
20
19
18
≤ 105 °C
j
Min
Max
0
16
62.5
—
25
—
0
3
13
—
40
—
6
—
VM
Unit
Notes
MHz
ns
ns
ns
ns
1
ns
ns
2
11
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