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Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)
Vdd = 3.3 ± 5% V dc, GND = 0 V dc, C
Num
7
Boundary-scan input data hold time
8
TCK to output data valid
9
TCK to output high impedance
10
TMS, TDI data setup time
11
TMS, TDI data hold time
12
TCK to TDO data valid
13
TCK to TDO high impedance
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Figure 5 provides the JTAG clock input timing diagram.
TCK
Figure 6 provides the TRST timing diagram
TCK
TRST
12
= 50 pF, 0 ≤ T
L
Characteristic
3
3
VM = Midpoint Voltage (1.4 V)
Figure 5. Clock Input Timing Diagram
.
5
Figure 6. TRST Timing Diagram
≤ 105 °C
j
Min
Max
27
—
4
25
3
24
0
—
25
—
4
24
3
15
1
2
VM
VM
VM
4
Unit
Notes
ns
2
ns
3
ns
3
ns
ns
ns
ns
2
VM
603 Hardware Specifications
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