Section 1.8, "System Design Information - Motorola PowerPC 603 Hardware Specifications

1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603.
1.8.1 PLL Configuration
The 603 PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
603 is shown in Table 11 for nominal frequencies.
PLL_CFG[0–3]
Bus-to-
Core
Multiplier
0000 1x
0001 1x
0010 1x
0100 2x
0101 2x
1000 3x
1001 3x
1100 4x
0011
1111
Notes:
1. The sample bus-to-core frequencies shown are for reference only.
2. Some PLL configurations may select bus, CPU, or PLL frequencies which are not supported by the 603; see
Section 1.4.2.2, "Input AC Specifications," for valid SYSCLK frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus
mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications
given in this document do not apply in PLL-bypass mode.
4. In clock-off mode, no clocking occurs inside the 603 regardless of the SYSCLK input.
5. PLL_CFG[0–1] signals select the CPU-to-bus ratio (1:1, 2:1, 3:1, 4:1), PLL_CFG[2–3] signals select the CPU-to-PLL
multiplier (x2, x4, x8).
603 Hardware Specifications
Table 11. PowerPC 603 Microprocessor PLL Configuration
CPU Frequency in MHz (VCO Frequency in MHz)
Core-to-
Bus
VCO
16.6 MHz
Multiplier
2x —
4x —
8x 16.6
(133)
2x —
4x 33.3
(133)
2x —
4x 50
(200)
2x 66.6
(133)
Bus Bus Bus
20 MHz 25 MHz 33.3 MHz
— — —
— — 33.3
(133)
20 25 —
(160) (200)
— — 66.6
(133)
40 50 —
(160) (200)
60 75 —
(120) (150)
60 — —
(240)
80 — —
(160)
PLL bypass
Clock off
Bus Bus Bus
40 MHz 50 MHz 66.6 MHz
— — 66.6
(133)
40 50 —
(160) (200)
— — —
80 — —
(160)
— — —
— — —
— — —
— — —
21