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The BT chip requires a 26MHz clock that is provided by an internal buffer in the RF Smarti DC+ IC. The buffer receives the
26MHz signal from a VCTCXO and is enabled by BT_CLK_REQ (PIO2). Once the BT IC is powered-up, the BT-CLK-REQ
signal will be pulled high by an internal pull-up. The BT-CLK-REQ line also goes to the SM-Power IC where it is used to
turnon the VRF2 supply (power for VCTCXO).
The Bluetooth IC reset is generated by the application processor (GPIO13). This is a logic low signal (~2.7V when high).
After power-up, Persistent Store-Key (PS-Keys) settings are sent to the Host Controller Interface (HCI) firmware to initialize
BLUETOOTH. These settings (PCM configuration, BT address, etc....) are stored in the OMAP memory and downloaded to
the BT IC upon initialization. The 6-byte Bluetooth Address will be programmed during manufacture.
The CSR Bluetooth IC has a Deep Sleep mode. In this mode, the 26MHz clock (BT-CLK-REQ goes low) and much of the
analog circuitry is shut down to save power. The BT IC will automatically enter this mode when idle (no BT activity detected).
The device's timing is maintained by an internal, 1kHz slow clock. The chip will wake every 1.28 seconds to check for BT
activity. When the host sends a packet to the BlueCore3 while it is in Deep Sleep, the activity on the UART will wake the IC.
Then, with the BCSP protocol, the packet is resent after a delay.
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PROVISIONAL ISSUE
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