Dmd Data Formatting; Dlp Block Diagram - BenQ MP611 Product Service Manual

2.2 DMD Data Formatting

DMD data formatting circuit consists of DDP ASIC, DAD1000, RAM and FLASH. Please see figure 6.
(1) The DDP ASIC combines the DLP
processing in the same device. The ASIC includes the front-end functions of Auto Lock, Motion-Adaptive
De-Interlacing, Spatial-Temporal Noise Reduction Filters, Edge-Preserving Scaling, Keystone Adjustment and
On-Screen Display.
(2) The DAD1000 analog ASIC creates the 16 reset lines that control the pixels on the DMD. The DAD1000 and the
support circuitry establish the 3 voltage levels that comprise the reset waveform. The DDP ASIC supplies the
timing information to the DAD1000 via the STROBE signal, and controls which of the 16 individual reset signals
will be output via the SR16ADDR (3:0) lines. The SR16SEL(1:0) signals select the correct voltage level (bias, offset
or reset) for the current transition.
(3) The RAM is used with the DDP ASIC for bit-plane storage and as an extensive workspace for de-interlacing, noise
reduction filters, and Auto Lock. Unlike other front-end ICs, no additional external RAM is needed for supporting
de-interlacing.
(4) The FLASH memory is used for program storage of both the TI generated APIs and drivers and the Application
code written by the project engineering staff.
data processing functions and high performance DLP
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Figure 6 DLP Block diagram
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front-end image
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