Example Code - Samsung S5PC110 Manual

S5PC110_UM

2.7.4 EXAMPLE CODE

2.7.4.1 TX Channel
The IIS TX channel provides a single stereo compliant output. The transmit channel can operate in master or
Slave mode. Data is transferred between the processor and the IIS controller via an APB access or a DMA
access.
The processor must write words in multiples of two (i.e. for left and right audio sample). The words are serially
shifted out timed with respect to the audio bitclk, SCLK and word select clock, LRCLK.
TX Channel has 64X32 bits wide FIFO where the processor or DMA can write upto 16 left/right data samples
after enabling the channel for transmission.
An Example sequence is as follows:
Ensure the Audio bus clock and CDCLK are coming correctly to the IIS controller and FLUSH the TX FIFO using
the TFLUSH bit in the I2SFIC Register (IIS FIFO Control Register).
Please ensure that IIS Controller is configured in one of the following modes.
• TX only mode
• TX/RX simultaneous mode
This can be done by programming the TXR bit in the I2SMOD Register (IIS Mode Register).
1. Then Program the following parameters according to the need
− MSS, RCLKSRC
− SDF
− BFS
− BLC
− LRP
For Programming, the above-mentioned fields please refer I2SMOD Register (IIS Mode Register).
2. Once ensured that the input clocks for IIS controller are up and running and step 1 and 2 have been
completed we can write to TX FIFO.
The write to the TX FIFO has to be carried out thorough the I2STXD Register (IIS TX FIFO Register)
This 32-bit data will occupy position 0 of the FIFO and any further data will be written to position 2, 3 and so
on.
2 IIS MULTI AUDIO INTERFACE
2-13