Audio Subsystem Clk Con - Samsung S5PC110 Manual

S5PC110_UM

1.6.2 AUDIO SUBSYSTEM CLK CON

To set the registers of audio subsystem CLK CON, refer to
1.6.2.1 Audio Subsystem Clock Source Register (Audio Subsystem CLK SRC, R/W, Address =
0xEEE1_0000)
AUDIO SUBSYSTEM
CLK SRC
Reserved
MUX
I2S_A
Reserved
CLKMUX_ASS
1.6.2.2 Audio Subsystem Clock Divider Register (Audio Subsystem CLK DIV, R/W, Address =
0xEEE1_0004)
AUDIO SUBSYSTEM
CLK DIV
Reserved
I2S_A_RATIO
AUDIO_BUS_CLK_
RATIO
Bit
[31:4] Reserved
[3:2] 10 = SCLK_AUDIO0
01 = IISCDCLK0 (from PAD)
00 = Main CLK
[1] This bit must be set as 0
[0] 1 = FOUT_EPLL
0 = XXTI
Bit
[31:8] Reserved
[7:4] Specifies the I2S_A clock divider ratio.
I2SCLK = MOUT
[3:0] Specifies the AUD_BUS clock divider ratio.
AUDIO_BUS_CLK = MOUT
Figure 1-3.
Description
Description
/ (I2S_A_RATIO+1)
I2S_A
/ (AUD_BUS_RATIO+1)
BUS
1 AUDIO SUBSYSTEM
Initial State
0
0
0
0
Initial State
0
0
0
1-9