Memory Subsystem; Section 2.3, "Memory Subsystem - IBM p5 590 System Handbook

pmcycles -m
Note: The pmcycles command is part of the bos.pmapi fileset. First check
whether that component is installed by using the lslpp -l bos.pmapi
command in AIX 5L.

2.3 Memory subsystem

The p5-590 and p5-595 memory controller is internal to the POWER5 chip. It
interfaces to four Synchronous Memory Interface II (SMI-II) buffer chips and eight
DIMM cards per processor chips as shown in Figure 2-4. There are 16 memory
card slots per processor book and each processor chip on an MCM owns a pair
of memory cards. The GX+ interface provides I/O subsystem connection.
3
The output of the lsattr command has been expanded with AIX 5L to include the processor clock
rate.
IBM Eserver p5 590 and 595 System Handbook
26
type powerPC_POWER5
frequency 165600000
smt_enabled true
smt_threads 2
state enable
(False, as used in this output, signifies that the value
cannot be changed through an AIX 5L command
interface.)
This command (AIX 5L Version 5.3 and later) uses the
performance monitor cycle counter and the processor
real-time clock to measure the actual processor clock
speed in MHz. This is the sample output of a 8-way
p5-590 running at 1.65 GHz system:
Cpu 0 runs at 1656 MHz
Cpu 1 runs at 1656 MHz
Cpu 2 runs at 1656 MHz
Cpu 3 runs at 1656 MHz
Cpu 4 runs at 1656 MHz
Cpu 5 runs at 1656 MHz
Cpu 6 runs at 1656 MHz
Cpu 7 runs at 1656 MHz
Processor type False
Processor Speed False
Processor SMT enabled False
Processor SMT threads False
Processor state False