Power4 And Power5 System Structures - IBM p5 590 System Handbook

symmetric multi-processor. Going beyond 32 processors with POWER4
architecture could increase interprocessor communication, resulting in higher
traffic on the interconnection fabric bus. This can cause greater contention and
negatively affect system scalability.
Moving the L3 cache reduces traffic on the fabric bus and enables POWER5
processor-based systems to scale to higher levels of symmetric
multi-processing. The POWER5 processor supports a 1.9 MB on-chip L2 cache,
implemented as three identical slices with separate controllers for each. Either
processor core can independently access each L2 controller. The L3 cache, with
a capacity of 36 MB, operates as a backdoor with separate buses for reads and
writes that operate at half the processor speed.
Because of the higher transistor density of the POWER5 0.13-
(over the original POWER4), it was possible to move the memory controller
on-chip and eliminate a chip that was previously needed for the memory
controller function. These changes in the POWER5 processor also have the
significant side benefits of reducing latency to the L3 cache and main memory, as
well as reducing the number of chips that are necessary to build a system.
The POWER5 processor supports the 64-bit PowerPC® architecture. A single
die contains two identical processor cores, each supporting two logical threads.
This architecture makes the chip appear as a four-way symmetric
multi-processor to the operating system. The POWER5 processor core has been
designed to support both enhanced simultaneous multi-threading and
single-threaded (ST) operation modes.
POWER4
Processor Processor
L2
cache
Fabric bus
Fabric bus
Fabric
controller
L3
cache
Memory
controller
Memory
Figure 2-1 POWER4 and POWER5 system structures
Processor Processor
L2
L3
cache
cache
Fabric bus
Fabric
controller
L3
cache
Memory
controller
Memory
POWER5
Processor Processor Processor
L2
cache
Fabric bus Fabric bus
Fabric
controller
Memory
controller
Memory
Chapter 2. Hardware architecture
m technology
µ
Processor
L2
L3
cache
cache
Fabric bus
Fabric
controller
Memory
controller
Memory
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