Dynamic Cpu Deallocation; Eeh On Power5 - IBM p5 590 System Handbook

PCI PCI
bridge bridge
PCI to PCI PCI to PCI
Figure 6-4 EEH on POWER5
The ultimate situation is to use only EEH-enabled PCI adapters, to eliminate
system and partition disruptions due to PCI bus errors, and merely suffer the loss
of a single PCI adapter if that adapter causes a PCI bus error. Most adapters
support EEH. EEH is part of the PCI 2.0 specification, although its
implementation is not required for PCI compliance.
For those older adapters that do not support EEH, special care should be taken
and documentation should be checked to ensure they are currently supported.
See 2.7.1, "EEH adapters and partitioning" on page 38 for more information.

6.5.2 Dynamic CPU Deallocation

Dynamic CPU Deallocation has been available since AIX Version 4.3.3 on
previous RS/6000 and pSeries systems, is the ability for a system to
automatically deconfigure an error prone CPU before it causes an unrecoverable
system error (unscheduled server outage). It is part of the p5-590 and p5-595
RAS features.
IBM Eserver p5 590 and 595 System Handbook
152
POWER5 POWER5
RIO bridge RIO bridge
X parity error (new)
PCI PCI
bridge bridge
(EADS) (EADS)
X parity error
PCI adapter PCI adapter
The IBM POWER5 systems
add additional recovery
features to handle potential
errors in the Processor Host
Bridge (PCI bridge), and the
GX+ bus adapter. These new
servers also support "hot" add
and removal of entire I/O
drawers. These features
provide improved diagnosis,
isolation, and management of
errors in the server I/O path
and new opportunities for
concurrent maintenance - to
allow faster recovery from I/O
path errors, often without
impact to system operation.