Memory Subsystem - IBM p5 590 System Handbook

Introduction to simultaneous multi-threading
Simultaneous multi-threading is a hardware design enhancement in POWER5
architecture that allows two separate instruction streams (threads) to execute
simultaneously on the processor. It combines the capabilities of superscaler
processors with the latency hiding abilities of hardware multi-threading.
Using multiple on-chip thread contexts, the simultaneous multi-threading
processor executes instructions from multiple threads each cycle. By duplicating
portions of logic in the instruction pipeline and increasing the capacity of the
register rename pool, the POWER5 processor can execute several elements of
two instruction streams, or threads, concurrently. Through hardware and
software thread prioritization, greater utilization of the hardware resources can
be realized without an impact to application performance.
The benefit of simultaneous multi-threading is realized more in commercial
environments over numeric intensive environments, since the number of
transactions performed outweighs the actual speed of the transaction. For
example, the simultaneous multi-threading environment would be much better
suited for a Web server or database server than it would be for a Fortran weather
prediction application. In the rare case that applications are tuned for optimal use
of processor resources there may be a decrease in performance due to
increased contention to cache and memory. For this reason simultaneous
multi-threading may be disabled.
Although it is the operating system that determines whether simultaneous
multi-threading is used, simultaneous multi-threading is otherwise completely
transparent to the applications and operating system, and implemented entirely
in hardware (simultaneous multi-threading is not supported on AIX 5L Version
5.2).

1.3.2 Memory subsystem

With the enhanced architecture of larger 7.6 MB L2 and 144 MB L3 caches, each
mutichip module (MCM) can stage information more effectively from processor
memory to applications. These caches allow the p5-590 and p5-595 to run
workloads significantly faster than predecessor servers.
The difference of memory hierarchy between POWER4 and POWER5 systems is
represented in Figure 1-4 as follows:
IBM Eserver p5 590 and 595 System Handbook
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