Edk Pcore Interface - Xilinx LogiCORE IP User Manual

Chapter 6: Control Interface

EDK pCore Interface

In contrast to GPP Mode and Constant Mode control interfaces, when you select this
control interface option in CORE Generator, no netlist is created. Instead, a database is
generated containing the necessary files for use in an EDK project. This database includes:
<component_name> -> drivers
-> pcores
For use in an EDK project:
1.
36
-> scaler_v3_01_a
-> axi_scaler_v4_00_a -> data
Copy the /drivers/scaler_v3_01_a sub-directory from the CORE Generator database
to the /drivers directory in your EDK project repository.
www.xilinx.com
-> data -> scaler_v2_1_0.mdd
scaler_v2_1_0.tcl
-> example -> example.c
-> src -> Makefile
xscaler.c
xscaler.h
xscaler_coefs.c
xscaler_g.c
xscaler_hw.h
xscaler_intr.c
xscaler_sinit.c
-> scaler_v2_1_0.mpd
scaler_v2_1_0.pao
-> hdl -> vhdl CoefsFIFO.vhd
->
coefs.vhd
CoefRAM.vhd
CoefMemBlk.vhd
HeartBeater.vhd
HPhaseAccumulator.vhd
HWT.vhd
ImageXLib_arch.vhd
ImageXLib_utils.vhd
MemXLib_arch.vhd
MemXLib_utils.vhd
Scaler.vhd
Scaler_RTI.vhd
Scaler_wrap0.vhd
Scaler_wrap0_core.vhd
ScalerExternalSM.vhd
syncgen_core.vhd
user_logic.vhd
v_scaler_v4_0.vhd
xscaler.vhd
YCCheckSum.vhd
Video Scaler v4.0 User Guide
UG805 March 1, 2011