Memory Mode - Xilinx LogiCORE IP User Manual

Example 8: Down-scaling 720P/60 YC4:2:2 to 640x480
45 kHz line rate
Vertical scale ratio = 0.6667
Horizontal scale ratio = 0.5
FLineIn = 45000
Single-engine implementation
Shrink-factor inputs:
This conversion will work in any of the supported devices and speed grades.
Example 9: Converting 720P/60 YC4:2:2 to 1080i/60 (1920x540)
45 kHz line rate
Vertical scale ratio = 0.75
Horizontal scale ratio = 1.5
FLineIn = 45000
Single-engine implementation
Shrink-factor inputs:
This conversion will work in Virtex-5, but not in Spartan-3A DSP since the MinF'clk is
greater than the Spartan-3A Fmax, but less than the Virtex-5 Fmax, as shown in
Table

Memory Mode

Using an input frame buffer allows you to stretch the processing time over the entire frame
period (utilizing the available blanking periods). New input lines may be provided as the
internal phase-accumulator dictates, instead of the input timing signals.
The critical factors may be summarized as follows:
•
•
Video Scaler v4.0 User Guide
UG805 March 1, 2011
CyclesRequiredPerOutputLine = 2*1280 + 150 (approximately)
MaxVHoldsPerInputAperture = round_up(480/720) = 1
MaxClksTakenPerVAperture = 2710 * 1 = 2710
MinF'clk' = 45000*2710 = 121.95 MHz
20
hsf=2 x (1/0.5) = 0x200000
20
vsf=2 x (1/0.6667) = 0x180000
CyclesRequiredPerOutputLine = 2*1920 + 150 (approximately)
MaxVHoldsPerInputAperture = round_up(540/720) = 1
MaxClksTakenPerVAperture = 3990 * 1 = 3990
MinF'clk' = 45000*3990 = 179.55 MHz
20
hsf=2 x (1/1.5) = 0x0AAAAA
20
vsf=2 x (1/0.6667) = 0x155555
9-1.
ProcessingOverheadPerLine – The number of extraneous cycles needed by the scaler
to complete the generation of one output line, in addition to the actual processing
cycles. This is required due to filter latency and State-Machine initialization. For all
cases in this document, this has been approximated as 50 cycles per component per
line.
FrameProcessingOverhead – The number of extraneous cycles needed by the scaler
to complete the generation of one output frame, in addition to the actual processing
cycles. This is required mainly due to vertical filter latency. For all cases in this
document, this has been generally approximated as 10000 cycles per frame.
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Memory Mode
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