Resource Utilization - Xilinx LogiCORE IP Product Manual

Resource Utilization
Resources required for the this core have been estimated for the devices shown in
Table 2-1, Table
were generated using Xilinx CORE Generator™ tools, v14.4. They are derived from
post-synthesis reports, and might change during MAP and PAR.
ISE Design Suite Resource Utilization Data
Table 2‐1: Resource Utilization for Virtex‐7 Families
SDI Channel
FEC Include
Number
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
LogiCORE IP SMPTE2022‐5/6 RX v2.1
PG033 December 18, 2012
2-2, Table 2-3, Table 2-4,
FFs
0 7994
0 10673
0 13368
0 16046
0 18721
0 21417
0 24053
0 26723
1 11524
1 14755
1 17934
1 21055
1 24353
1 27469
1 30730
1 33815
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Chapter 2: Product Specification
Table 2-5, Table 2-6, and
LUTs Slices LUT FF Pairs
5869 2928
8331 3942 13234
9697 4898 16358
10574 5795 19557
13639 7417 24273
13851 7711 25786
15003 9487 30539
15518 9845 32582
8654 4047 13470
11643 5966 18597
13670 6375 21355
14788 7019 24325
18552 10023 31544
19706 10020 33161
21267 12060 39081
20955 13566 42385
Table 2-7. These values
36k 18k
BRAM BRAM
9802 14 3
21 5
28 7
35 9
42 11
49 13
56 15
63 17
44 7
51 11
72 15
79 22
114 28
121 33
128 38
135 43
10