Output Data And Timing Signals - Xilinx LogiCORE IP User Manual

Chapter 4: Video I/O Interface and Timing

Output Data and Timing Signals

Although driving the scaler input using a direct standard video feed is supported, the
equivalent cannot be said for the scaler output. Because of the bursty nature of the vertical
filter portion of the scaling operation, the required size of the output buffering would be
prohibitive. This would be more aptly targeted to an external memory interface, which is
beyond the scope of this LogiCORE™ IP. However, the user may decide that his system
can directly handle the bursty data output from the scaler, provided valid data is indicated
by the core. Consequently, simple hand-shaking is achieved using the video_out_we and
video_out_almost_full signals.
When a line of data becomes available in the output buffer, and the
video_out_almost_full flag is low, the video_out_we flag is asserted as shown in
Figure
X-Ref Target - Figure 4-5
The video_out_almost_full input is provided to throttle the output from the scaler.
When this is asserted high for a number of line periods, the line_request signal will be
deasserted due to back-pressure through the scaler. If video_out_almost_full is low
at the start of an output line, the entire line will be delivered. The target must de-assert
video_out_almost_full when it is ready to accept the entire line.
Upon completion of the final line requested according to the output_v_size parameter,
the scaler will send a pulse of six video_out_clk cycles on the output_frame_done
signal.
For 4:2:0 outputs, the valid chroma data output will be accompanied by a high level on the
chroma_out signal as shown in
X-Ref Target - Figure 4-6
28
4-5, and data is driven out.
Figure 4-5: Scaler Output Timing (8-bits YC4:2:2/4:2:0)
video_data_out (7:0) (Luma)
video_data_out (15:8) (Chroma)
chroma_out
Figure 4-6: Scaler 4:2:0 Output Validation (8-bits)
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Figure 4-6.
Line1 Line2
Valid N/V
Line3 Line4
Valid N/V
UG678_5-5_081809
Video Scaler v4.0 User Guide
UG805 March 1, 2011