Overview; Features; Fpga I/O Registers - Advantech MIC-3396 User Manual

C.1

Overview

Advantech BMC solution combines a NXP LPC1768 ARM Cortex-M3 based 32-bit
microcontroller and a Lattice XP2 series FPGA. The FPGA mainly integrates hard-
ware interfaces which are not available or not available in the right amount inside the
LPC1768, like I
As the MIC-3396 will be available in versions both with and without the BMC, some
functions will be implemented redundant inside the FPGA and BMC. If the BMC is
populated, a simple register inside the FPGA is used to control the regarding function
from the BMC. On a MIC-3396 without BMC the FPGA controls the function by itself
in the same way as before.
C.2

Features

 Drone Mode
 Hot-Swap: Hot insertion and removal control
 CompactPCI Backplane: CompactPCI slot Addressing
 LPC Interface: Provides LPC Bus access
 KCS Interface: Standard IPMI payload interface from x86 to BMC
 Watchdog
 Debug Message: Boot time POST message
C.3

FPGA I/O Registers

The Advantech MIC-3396 FPGA communicates with main I/O spaces. The LPC unit
is used to interconnect the Intel QM87 LPC signals. The Debug Port Unit is used to
decode POST codes. The Hot-Swap Out-Of-Service LED Control Unit is used to con-
trol the blue LED during Hot-Insert and Hot-Remove. The Drone Mode Unit is used to
disable the CPCI Bridge. The other signals in the Miscellaneous Unit are for interfac-
ing with corresponding I/O interface signals.
Table C.1: LPC I/O registers address
LPC Address
0x 80
0x440
0x442
0x443 ~ 0x444
0x445
0x446
0x447
0x448
0x44A
0x44C
0x44F
0x4A0 ~ 0x4A7
0x4B0 ~ 0x4B8
0xCA2 ~ 0xCA3
MIC-3396 User Manual
2
C or KCS.
I/O Type Description
W Port 80 Display
R FPGA Minor Version
R UART_MUX Switch
RW Watchdog Register
R FPGA Major Version
R BIOS Flash Control
R Geographical Address (GA)
R HW Revision
RW GPIO Control
R FPGA ID
RW Scratch Register
RW I2C Interface & Control
RW SPI Interface & Control
RW KCS Interface
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