Introduction; Terms And Definitions - Advantech MIC-3396 User Manual

3.1

Introduction

The MIC-3396 fully supports the major IPMI 2.0 interface and the PICMG 2.9 R1.0
specification. The BMC solution is based on the Advantech IPMI Core G02 and it is
designed around a combination of a NXP LPC1768 ARM Cortex-M3 based 32 bit
microcontroller and a Lattice MachXO2 series FPGA.
The microcontroller is running FreeRTOS as basic OS, with Advantech's own hard-
ware abstraction layer (HAL) and IPMI stack.
The BMC's key features and functions are listed below.
Advantech Integrity Sensor
Based on Advantech IPMI Core, designed for CPCI
 IPMI 2.0 Specification compliant
 IPMI-over-LAN
 Serial-over-LAN
 KCS interface for direct IPMI communication between Operating System and
BMC
 Full BMC watchdog support as defines in IPMI specification
 System Event Log (SEL)
 HPM.1 for in field updates, supporting:
– Bootloader
– Firmware
– FPGA
– BIOS
 Automatic UART muxing between all serial interfaces for easy console access
 Additional sensors for hardware monitoring
3.2

Terms and Definitions

Term
AMC
API
ATCA
BIOS
BMC
CLI
CPCI
CPU
DDR3
DIMM
DIP
EEPROM
EMAC
FLASH
FPGA
FRU
GbE
GPIO
HPM.1
MIC-3396 User Manual
Definition
Advanced Mezzanine Card
Application Programming Interface
Advanced Telecommunications Computing Architecture
Basic Input/Output System
Baseboard Management Controller
Command Line Interface
CompactPCI
Central Processing Unit
Double Data Rate 3
Dual In-line Memory Module
Dual In-line Package
Electrically Erasable Programmable Read Only Memory
Ethernet Media Access Controller
Flash memory
Field Programmable Gate Array
Field Replaceable Unit
Gigabit Ethernet
General Purpose Input / Output
Hardware Platform Management.1
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