Dram Clock; Dram Timing; Sdram Cas Latency - Acorp 7KT333 User Manual

Bhapter 1 Bhapter 1
Bhapter 1 Bhapter 1 Bhapter 1

DRAM Clock

This item determines DRAM Clock following the CPU
host clock.
The Choices: By SPD(default), 100.

DRAM Timing

The DRAM timing is controlled by the DRAM Timing
Registers. The Timings programmed into this register are
dependent on the system design.
The Choices: By SPD(default), Manual.

SDRAM CAS Latency

2.5 (default)
2
Bank Interleave
The Choices: Disabled(default), 2 Bank, 4 Bank.
Precharge to Active (Trp)
The Choices: 3T(default), 2T.
Active to Precharge
6T (default)
5T
Active to CMD (Trcd)
The Choices: 3T(default), 2T.
DRAM Queue Depth
The Choices: 4 Level(default), 2 Level, 3 Level.
DRAM Command Rate
The Choices: 2T Command(default), 1T Command.
Set SDRAM latency Time to
2.5.
Set SDRAM latency Time to 2.
Set DRAM Precharge in 6.
Set DRAM Precharge in 5.
1 - 1 5 1 - 1 5 1 - 1 5 1 - 1 5 1 - 1 5
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