Mitsubishi DPLUS 74SB -BKA Service Manual page 141

All functions of the LM1269 are controlled through the I²C Bus. Details on the internal registers are covered in the I²C Interface
Registers Section. Figure 1 shows the block diagram of the
LM1269. The I²C signals come in on pins 11 and 12 and go to the
I²C Interface. Both the internal blocks with an "R" and the four
external DACs are controlled by the I²C Interface. The video and
OSD block are shown for the red channel in Figure 1. The blocks
for both the green and blue channels are not shown; however,
they are identical to the red channel.
Proper operation of the LM1269 does require a very accurate
reference voltage. This voltage is generated in the V
insure an accuate voltage over temperature, an external resistor
is used to set the current in the V
is connected to pin 10. This resistor should be 1% and have a
temperature coefficient under 100 ppm/
MUST BE KEPT AWAY FROM PIN 10. This pin has a very high
input impedance and will pick up any high frequency signals
routed near it. The board layout shown in Figure 10 is a good
example of trace routing near pin 10. The output of the V
goes to a number of blocks in the video section and also to pin 21.
This pin allows capacitor filtering on the V
accurate external reference. A buffer must be used with this
reference, the maximum current loading should be only 100 µA.
Note: Any noise injected into pin 21 will appear on the video. The voltage
reference must be kept very clean for best performance of the
LM1269.
The video inputs are pins 5, 6, and 7. Looking at the red channel
(pin 5) note that the "Clamp DC Restore Amp" is connected to this
pin. Since the video must be AC coupled to the LM1269, the
coupling cap is also used to store the reference voltage for DC
restoration. The "Clamp DC Re-store Amp" block charges the
input capacitor to the correct voltage when the clamp pulse (pin
23) is active. The "Hi Z Input Buffer Amp" buffers the video signal
for internal processing. Input impedance to this stage is typically
20 MW. With such a high impedance the DC restoration can appear
to be working for a number of minutes after the clamp pulse in
removed.
The output of the Buffer Amp goes to the Contrast stage. The 7 bit
contrast register (03h) sets the contrast level through the I²C
bus. This register controls the Contrast stage in each video chan-
nel. Contrast adjustment range is up to –20 dB. Loading all zeros
in the contrast register gives –20 dB attenuation. All ones will
give no attenuation. The output of this stage is used as the feed-
back for the DC restoration loop. "Auto Beam Limit Amp" or ABL is
the next block in the video path. This is a voltage controlled gain
stage which gives no attenuation with 5V at pin 22 and gives
about –10 dB attenuation with 2V at pin 2. ABL is covered in more
detail later in this section.
Next in the video path is the "OSD Mixer". The OSD Select signal
at pin 4 controls this stage, selecting OSD with a high at pin 4, and
video with a low at pin 4. Since the DC restoration feedback is at
the Contrast output, the video black level will match the OSD black
level. The OSD signal is mixed with the video signal at the output
of this stage.
The OSD goes through the "OSD Contrast" stage before entering
the "OSD Mixer" block. Bits 3 and 4 of register 08h control the
block. To
Ref
stage. The external resistor
Ref
C. ALL VIDEO SIGNALS
o
stage
Ref
output and offers an
Ref
OSD contrast giving four video levels for the OSD window. Maxi-
mum video level for the OSD window occurs with both bits set to
one. Minimum video level will occur with both bits set to a zero.
Following the "OSD Mixer" is the "Gain" block. Each video channel
has its own independent control of this block so the user can
balance the color of the CRT display. Registers 00h, 01h, 02h are
used for the gain attenuation. These registers are 7 bits with the
maximum attenuation of –10 dB occurring when all zeros are
loaded.
The final block in the video path is the "Output Buffer Amp".
This stage provides the drive needed for the inputs of a CRT
driver. The recommended driver for this pre-amp is one of the
LM246X family. Horizontal blanking is also added to the video
signal from the "H Blank" stage. This block is covered in more
detail below. DC offset of the output is set by the "DC DACs
Offset" stage. Bits 0 through 2 in register 08 control this stage.
This gives 8 different black levels ranging from 0.75V to 1.55V.
When using one of the LM246X CRT driver family it is recom-
mended that the black level be set to 1.25V.
ABL: The Auto Beam Limit control reduces the gain of the video
amplifiers in response to a control voltage proportional to the
CRT beam current. The ABL acts on all three channels in an
identical manner. This is required for CRT life and X-ray
protection. The beam current limit circuit application is as shown
in Figure 4: when no current is being drawn by the EHT supply,
current flows from the supply rail through the ABL resistor and
into the ABL input of the IC. The IC clamps the input voltage to
a low impedance voltage source (the 5V supply rail).
When current is drawn from the EHT supply, some of the cur-
rent passing through the ABL resistor goes to the EHT supply,
which reduces the current flowing into the ABL input of the IC.
When the EHT current is high enough, the current flowing into
the ABL input of the IC drops to zero. This current level deter-
mines the ABL threshold and is given by:
I
Where:
V is the external supply (usually the CRT driver supply rail, about
S
80V)
V is the threshold ABL voltage of the IC
ABL TH
R is the ABL resistor value
ABL
I is the ABL limit
ABL
When the voltage on the ABL input drops below the ABL thresh-
old of the pre-amp the gain of the pre-amp reduces, which re-
duces the beam current. A feedback loop is thus established
which acts to prevent the average beam current exceeding I
H Flyback: H Flyback is an analog signal input from the monitor
horizontal scan. The "H Blank" section uses this signal to add
7-40
−
V V
S ABLTH
=
ABL
R
ABL
.
ABL