Mitsubishi DPLUS 74SB -BKA Service Manual page 111

40 41 39 38 PWM3
41 42 40 39 HIN
42 43 41 40 VIN
43 - - - NC
44 44 42 - D-
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU wiht 16-bit address bus and 8-bit data bus operates at 6MHz.The non-
maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher priority.
The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.
Please refer the 6502 reference menu for more detail.
RAM
The 1024 bytes SRAM include:
128 bytes SRAM are from $0080H to $00FFH
256 bytes SRAM are from $0100H to $01FFH
256 bytes SRAM are from $0200H to $02FFH
256 bytes SRAM are from $0300H to $03FFH
128 bytes SRAM are from $0400H to $047FH
The 256 bits bit-addressable SRAM are from $0500H to $05FFH
Flash Memory
60K bytes flash memory for program. Address is located from $1000 to $FFFFh.
The following addresses are reserved for special purpose:
$FFFAh (low byte) and $FFFBh (high byte): INT0 interrupt vector.
$FFFCh (low byte) and $FFFDh (high byte): program reset interrupt vector.
I/O PWM3 output (10V open-drain)
I Hsync input.
I Vsync input.
No Connection.
I/O USB D-signal.
7-10
WT62P2 v1.04
USB Monitor Controller