Mitsubishi DPLUS 74SB -BKA Service Manual page 113

RESET/3V3
Watchdog Timer Reset
VDD
Address
Illegal Address Reset
6MHz
Memory Mapping
External Reset
A low level on the RESET/3.3V pin will generate reset.
Illegal address Reset
When the address bus of CPU goes to illegal address, a reset pulse will be generated.
The illegal address is defined as $0040h~$007Fh, $0300h~$0FFEh and $1000h~$7FFFh.
Low VDD Voltage Reset
When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after
the voltage is higher than 3.9V.
Watchdog Timer Reset
If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer watchdog
timer section for more information.
Low VDD Reset
Fig. 1 Reset Signals
7-12
LATCH
R
Peripheral
Circuits
2.048ms
Timer
CPU