Mitsubishi DPLUS 74SB -BKA Service Manual page 117

Free-running sync signal and self-test pattern
The self-generated free run sync signals are output from HOUT and VOUT pins when ENFREE bit is set.
Four kinds of standard VESA timings are selected by FREE1 and FREE0 bits.
Self-test pattern signal is output form PAT pin when ENPAT bit is set. PAT1 and PAT0 bits select different
self-test pattern.
PAT1 = 0, PAT0 = 0
F Hot frequency
H
F Ver frequency
V
T Hor total time
HT
T Ver total time
VT
T H sync time
HS
H Back porch +
T
HB
H Left border
H Front porch +
T
HF
H Right border
T V sync time
VS
V Back porch +
T
VB
V Top border
V Front porch +
T
VF
V Bottom border
T Video pulse width
VIDEO
PAT1 = 0, PAT0 = 1
Fig. 7 Test Pattern
X00 X01
31.496kHz 48kHz
59.993Hz 72.072Hz
31.75us 20.833us
16.669ms 13.875ms
3.833us 2.417us
2 us 1.417us
0.708us 1.125us
2 × T 6 × T
HT
33 × T 23 × T
HT
11 × T 38 × T
HT
41.67ns 41.67ns
Fig.8 Free-running sync signal and test pattern timing
PAT1 = 1, PAT0 = 0
010
63.83kHz 81.25kHz
59.878Hz 64.865Hz
15.667us 12.333us
16.7ms 15.417ms
1us 1.083us
2.417us 1.833us
0.542us 0.375us
3 × T 3 × T
HT HT
38 × T 46 × T
HT HT
3 × T 2 × T
HT HT
41.67ns 41.67ns
7-16
PAT1 = 1, PAT0 = 1
011 110
90.909kHz 106.195kHz
84.8Hz
11us
11.792ms
1us
1.583us
0.375us
3 × T
HT HT
44 × T
HT HT
2 × T
HT HT
41.67ns
111
84.96Hz
9.417us
11.771ms
0.833us
1.417us
0.292us
3 × T
HT
46 × T
HT
2 × T
HT
41.67ns