Atmel ATmega8535L User Manual page 90

Registers
ATmega8535(L)
90
Figure 40. 16-bit Timer/Counter Block Diagram
Direction
Timer/Counter
TCNTn
=
OCRnA
=
OCRnB
ICRn
TCCRnA
Note: 1. Refer to Figure 1 on page 2, Table 26 on page 60, and Table 32 on page 64 for
Timer/Counter1 pin placement and description.
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture
Register (ICR1) are all 16-bit registers. Special procedures must be followed when
accessing the 16-bit registers. These procedures are described in the section "Access-
ing 16-bit Registers" on page 92. The Timer/Counter Control Registers (TCCR1A/B) are
8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to
Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).
All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).
TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T1 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR1A/B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the
(1)
Count
Clear
Control Logic
clk
Tn
TOP BOTTOM
= =
0
Fixed
TOP
Values
ICFn (Int.Req.)
Edge
Detector
TCCRnB
).
T 1
TOVn
(Int.Req.)
Clock Select
Edge
Tn
Detector
( From Prescaler )
OCnA
(Int.Req.)
Waveform
OCnA
Generation
OCnB
(Int.Req.)
Waveform
OCnB
Generation
( From Analog
Comparator Ouput )
Noise
Canceler
ICPn
2502K–AVR–10/06