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Atmel ATmega8535L User Manual

Atmel ATmega8535L User Manual

8-bit avr microcontroller with 8k bytes in-system programmable flash

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Features

•

High-performance, Low-power AVR

•

Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

•

Nonvolatile Program and Data Memories

– 8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM

– Programming Lock for Software Security

•

Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels for TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP

Package Only

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•

Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

•

I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF

•

Operating Voltages

– 2.7 - 5.5V for ATmega8535L

– 4.5 - 5.5V for ATmega8535

•

Speed Grades

– 0 - 8 MHz for ATmega8535L

– 0 - 16 MHz for ATmega8535

®

8-bit Microcontroller

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

ATmega8535

ATmega8535L

2502K–AVR–10/06

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Summary of Contents for Atmel ATmega8535L

Page 1 – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 • Speed Grades – 0 - 8 MHz for ATmega8535L – 0 - 16 MHz for ATmega8535 2502K–AVR–10/06...
Page 2: Pin Configurations
Pin Configurations Figure 1. Pinout ATmega8535 (XCK/T0) PB0 PA0 (ADC0) (T1) PB1 PA1 (ADC1) (INT2/AIN0) PB2 PA2 (ADC2) (OC0/AIN1) PB3 PA3 (ADC3) (SS) PB4 PA4 (ADC4) (MOSI) PB5 PA5 (ADC5) (MISO) PB6 PA6 (ADC6) (SCK) PB7 PA7 (ADC7) RESET AREF AVCC XTAL2 PC7 (TOSC2)
Page 3: Block Diagram
ATmega8535(L) Overview The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
Page 4 In Extended Standby mode, both the main Oscillator and the asynchro- nous timer continue to run. The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
Page 5 ATmega8535(L) Pin Descriptions Digital supply voltage. Ground. Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.
Page 6 Resources A comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. ATmega8535(L) 2502K–AVR–10/06...
Page 7 ATmega8535(L) About Code This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is Examples included before compilation. Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling in C is compiler dependent.
Page 8 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
Page 9 ATmega8535(L) Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash pro- gram memory.
Page 10 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference.
Page 11 ATmega8535(L) General Purpose The Register File is optimized for the AVR Enhanced RISC instruction set. In order to Register File achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input •...
Page 12 The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
Page 13 ATmega8535(L) Instruction Execution This section describes the general access timing concepts for instruction execution. The Timing AVR CPU is driven by the CPU clock clk , directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
Page 14 also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 224. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
Page 15 ATmega8535(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ;...
Page 16 AVR ATmega8535 This section describes the different memories in the ATmega8535. The AVR architec- ture has two main memory spaces, the Data Memory and the Program Memory space. Memories In addition, the ATmega8535 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
Page 17 ATmega8535(L) SRAM Data Memory Figure 9 shows how the ATmega8535 SRAM Memory is organized. The 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 512 locations address the internal data SRAM.
Page 18 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as described in Figure Figure 10. On-chip Data SRAM Access Cycles Address Address valid Compute Address Data Data...
Page 19 ATmega8535(L) The EEPROM Address Register – EEARH and EEARL – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8535 and will always read as zero. •...
Page 20 value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1.
Page 21 ATmega8535(L) The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software.
Page 22 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ;...
Page 23 ATmega8535(L) E E P R O M d a t a c o r r u p t i o n c a n e a s i l y b e a v o i d e d b y f o l l o w i n g t h i s d e s i g n recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply volt- age.
Page 24 System Clock and Clock Options Clock Systems and their Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the Distribution clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes”...
Page 25 ATmega8535(L) Asynchronous Timer Clock – The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. ADC Clock –...
Page 26 This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators.
Page 27 ATmega8535(L) The CKSEL0 fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Additional Delay Power-down and from Reset CKSEL0 SUT1..0 Power-save = 5.0V) Recommended Usage 258 CK...
Page 28 Low-frequency Crystal To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- Oscillator quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors.
Page 29 At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre- quency within ± 3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given V and Temperature.
Page 30 Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Start-up Time from Power- Additional Delay from SUT1..0 down and Power-save Reset (V = 5.0V) Recommended Usage 6 CK – BOD enabled 6 CK 4.1 ms Fast rising power 6 CK 65 ms Slowly rising power...
Page 31 ATmega8535(L) External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND.
Page 32 Power Management Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the and Sleep Modes power consumption to the application’s requirements. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
Page 33 ATmega8535(L) Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating.
Page 34 asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk , allowing operation only of asyn- chronous modules, including Timer/Counter2 if clocked asynchronously. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode.
Page 35 ATmega8535(L) Minimizing Power There are several issues to consider when trying to minimize the power consumption in Consumption an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating.
Page 36 System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Page 37 ATmega8535(L) Figure 15. Reset Logic DATA BUS MCU Control and Status Register (MCUCSR) Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL Pull-up Resistor Spike Reset Circuit Filter Watchdog Timer Watchdog Oscillator Delay Counters Clock Generator TIMEOUT CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol Parameter Condition...
Page 38 The test is performed using BODLEVEL = 1 for ATmega8535L and BODLEVEL = 0 for ATmega8535. BODLEVEL = 1 is not applicable for ATmega8535. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
Page 39 ATmega8535(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage –...
Page 40 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period . Refer to page 41 for details on operation of the Watchdog Timer. TOUT Figure 20.
Page 41 ATmega8535(L) Internal Voltage ATmega8535 features an internal bandgap reference. This reference is used for Brown- Reference out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference Enable The voltage reference has a start-up time that may influence the way it should be used.
Page 42 Table 17. WDT Configuration as a Function of the Fuse Settings of S8538C and WDTON How to Safety WDT Initial How to Disable Change S8535C WDTON Level State the WDT Time-out Unprogrammed Unprogrammed Disabled Timed Timed sequence sequence Unprogrammed Programmed Enabled Always enabled Timed...
Page 43 ATmega8535(L) if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow- ing procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.
Page 44 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: ;...
Page 45 ATmega8535(L) Timed Sequences for The sequence for changing the Watchdog Timer configuration differs slightly between Changing the the three safety levels. Separate procedures are described for each level. Configuration of the Watchdog Timer Safety Level 0 This mode is compatible with the Watchdog operation found in AT90S8535. The Watch- dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
Page 46 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega8535. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Interrupt Vectors in Table 19. Reset and Interrupt Vectors ATmega8535 Vector Program...
Page 47 ATmega8535(L) Table 20. Reset and Interrupt Vectors Placement BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 0x0000 0x0001 0x0000 Boot Reset Address + 0x0001 Boot Reset Address 0x0001 Boot Reset Address Boot Reset Address + 0x0001 Note: 1. The Boot Reset Address is shown in Table 93 on page 235. For the BOOTRST Fuse “1”...
Page 48 AddressLabels Code Comments 0x000 RESET: r16,high(RAMEND) ; Main program start 0x001 SPH,r16 ; Set Stack Pointer to top of RAM 0x002 r16,low(RAMEND) 0x003 SPL,r16 0x004 ; Enable interrupts 0x005 <instr> xxx .org 0xC01 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ;...
Page 49 ATmega8535(L) Moving Interrupts Between The General Interrupt Control Register controls the placement of the Interrupt Vector Application and Boot Space table. General Interrupt Control Register – GICR INT1 INT0 INT2 – – – IVSEL IVCE GICR Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
Page 50 Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section r16, (1<<IVSEL) out GICR, r16 C Code Example void Move_interrupts(void) /* Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL);...
Page 51 ATmega8535(L) I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Page 52 Ports as General Digital The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 23. General Digital I/O DDxn RESET PORTxn RESET SLEEP SYNCHRONIZER PINxn WDx: WRITE DDRx PUD:...
Page 53 ATmega8535(L) 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the dif- ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports.
Page 54 ceeding positive clock edge. As indicated by the two arrows t and t , a single pd,max pd,min signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25.
Page 55 ATmega8535(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Page 56 when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
Page 57 ATmega8535(L) Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 26 shows how the port pin control signals from the simplified Figure 23 can be overrid- den by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR micro- controller family.
Page 58 Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 22. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name...
Page 59 ATmega8535(L) Special Function IO Register – SFIOR ADTS2 ADTS1 ADTS0 – ACME PSR2 PSR10 SFIOR Read/Write Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Page 60 Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/ADC3 PA2/ADC2 PA1/ADC1 PA0/ADC0 PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV – – – – ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 26.
Page 61 ATmega8535(L) • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5.
Page 62 Table 27. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD DDOE SPE •...
Page 63 ATmega8535(L) TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin.
Page 64 Table 31. Overriding Signals for Alternate Functions in PC1..PC0 Signal Name PC1/SDA PC0/SCL PUOE TWEN TWEN PUOV PORTC1 • PUD PORTC0 • PUD DDOE TWEN TWEN DDOV SDA_OUT SCL_OUT PVOE TWEN TWEN PVOV DIEOE DIEOV – – SDA INPUT SCL INPUT Note: 1.
Page 65 ATmega8535(L) (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B.
Page 66 Table 34. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PD3/INT1 PD2/INT0 PD1/TXD PD0/RXD PUOE TXEN RXEN PUOV PORTD0 • PUD DDOE TXEN RXEN DDOV PVOE TXEN PVOV DIEOE INT1 ENABLE INT0 ENABLE DIEOV INT1 INPUT INT0 INPUT – –...
Page 67 ATmega8535(L) Port B Input Pins Address – PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write Initial Value Port C Data Register – PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/Write Initial Value Port C Data Direction Register –...
Page 68 External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
Page 69 ATmega8535(L) The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 36. The value on the INT0 pin is sampled before detecting edges.
Page 70 The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
Page 71 ATmega8535(L) 8-bit Timer/Counter0 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: with PWM • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator •...
Page 72 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Wave- form Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0).
Page 73 ATmega8535(L) Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk ). clk can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0).
Page 74 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
Page 75 ATmega8535(L) Compare Match Output The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- Unit tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 30 shows a simplified schematic of the logic affected by the COM01:0 bit setting.
Page 76 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
Page 77 ATmega8535(L) when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match.
Page 78 Figure 32. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn (COMn1:0 = 2) (COMn1:0 = 3) Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value.
Page 79 ATmega8535(L) Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
Page 80 OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: clk_I/O ----------------- - ⋅ OCnPCPWM N 510 The “N” variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Page 81 ATmega8535(L) Figure 35. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 36 shows the setting of OCF0 in all modes except CTC mode. Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk_I/O (clk TCNTn...
Page 82 Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC) OCRn OCFn ATmega8535(L) 2502K–AVR–10/06...
Page 83 ATmega8535(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0 Read/Write Initial Value • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode.
Page 84 When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 40 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 40. Compare Output Mode, non-PWM Mode COM01 COM00 Description...
Page 85 ATmega8535(L) • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 43. Clock Select Bit Description CS02 CS01 CS00 Description No clock source (Timer/counter stopped). /(No prescaling) /8 (From prescaler) /64 (From prescaler) /256 (From prescaler)
Page 86 • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register –...
Page 87 ATmega8535(L) Timer/Counter0 and Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter1 both Timer/Counter1 and Timer/Counter0. Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Page 88 Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f < f /2) given a 50/50% duty cycle. Since ExtClk clk_I/O the edge detector uses sampling, the maximum frequency of an external clock it can...
Page 89 ATmega8535(L) 16-bit The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • True 16-bit Design (i.e., Allows 16-bit PWM) • Two Independent Output Compare Units • Double Buffered Output Compare Registers •...
Page 90 Figure 40. 16-bit Timer/Counter Block Diagram Count TOVn (Int.Req.) Clear Control Logic Clock Select Direction Edge Detector BOTTOM ( From Prescaler ) Timer/Counter TCNTn OCnA (Int.Req.) Waveform OCnA Generation OCRnA OCnB Fixed (Int.Req.) Values Waveform OCnB Generation OCRnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge...
Page 91 ATmega8535(L) Waveform Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 98. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request.
Page 92 Accessing 16-bit The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR Registers CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access.
Page 93 ATmega8535(L) The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: ; Save Global Interrupt Flag r18,SREG ;...
Page 94 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: ; Save Global Interrupt Flag r18,SREG ;...
Page 95 ATmega8535(L) Timer/Counter Clock The Timer/Counter can be clocked by an internal or an external clock source. The clock Sources source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers”...
Page 96 TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 101. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits.
Page 97 ATmega8535(L) byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register.
Page 98 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
Page 99 ATmega8535(L) sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not the case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
Page 100 Compare Match Output The Compare Output Mode (COM1x1:0) bits have two functions. The waveform genera- Unit tor uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Fig- ure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.
Page 101 ATmega8535(L) A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits.
Page 102 Figure 45. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (COMnA1:0 = 1) (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value.
Page 103 ATmega8535(L) High frequency allows physically small sized external components (coils, capacitors), hence reducing total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
Page 104 The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ing at 0x0000 before the Compare Match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register.
Page 105 ATmega8535(L) OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution can be calculated in bits by using the following equation: ---------------------------------- - 2 ( ) PCPWM In phase correct PWM mode, the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
Page 106 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
Page 107 ATmega8535(L) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direc- tion.
Page 108 In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 47 on page 111).
Page 109 ATmega8535(L) Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk_I/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode, the OCR1x Register is updated at BOTTOM.
Page 110 Figure 52. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP - 1 TOP - 2 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value...
Page 111 ATmega8535(L) Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 46. Compare Output Mode, Fast PWM COM1A1/ COM1A0/ COM1B1 COM1B0 Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation).
Page 112 Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 48. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes.
Page 113 ATmega8535(L) Timer/Counter1 Control Register B – TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
Page 114 Timer/Counter1 – TCNT1H and TCNT1L TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit tempo- rary high byte register (TEMP).
Page 115 ATmega8535(L) Timer/Counter Interrupt Mask Register – TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK Read/Write Initial Value Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
Page 116 Timer/Counter Interrupt Flag Register – TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write Initial Value Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
Page 117: Asynchronous Operation
ATmega8535(L) 8-bit Timer/Counter2 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: with PWM and • Single Channel Counter Asynchronous • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) Operation •...
Page 118 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Page 119 ATmega8535(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 54 shows a block diagram of the counter and its surrounding environment. Figure 54. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear Oscillator...
Page 120 Figure 55. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn (8-bit Comparator ) OCFn (Int.Req.) bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the pulse width modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
Page 121 ATmega8535(L) Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. Compare Match Output The Compare Output mode (COM21:0) bits have two functions. The Waveform Genera- tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Unit Compare Match.
Page 122 A change of the COM21:0 bits state will take effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have an immediate effect by using the FOC2 strobe bits. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits.
Page 123 ATmega8535(L) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOT- TOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
Page 124 Figure 58. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn (COMn1:0 = 2) (COMn1:0 = 3) Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value.
Page 125 ATmega8535(L) Phase Correct PWM Mode The Phase Correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
Page 126 between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: clk_I/O ----------------- - ⋅ OCnPCPWM N 510 The “N” variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Page 127 ATmega8535(L) Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 62 shows the setting of OCF2 in all modes except CTC mode. Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk_I/O (clk TCNTn...
Page 128 Figure 63. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (f clk_I/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC) OCRn OCFn 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21...
Page 129 ATmega8535(L) Table 51. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter Mode Update of TOV2 Flag Mode (CTC2) (PWM2) of Operation OCR2 Set on Normal 0xFF Immediate PWM, Phase Correct 0xFF BOTTOM OCR2 Immediate Fast PWM 0xFF BOTTOM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def- initions.
Page 130 Table 54 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 54. Compare Output Mode, Phase Correct PWM Mode COM21 COM20 Description Normal port operation, OC2 disconnected. Reserved Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when down-counting.
Page 131 ATmega8535(L) Output Compare Register – OCR2 OCR2[7:0] OCR2 Read/Write Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. Asynchronous Operation of the Timer/Counter Asynchronous Status...
Page 132 Asynchronous Operation of When Timer/Counter2 operates asynchronously, some considerations must be taken. Timer/Counter2 • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1.
Page 133 ATmega8535(L) down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake-up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
Page 134 Timer/Counter Interrupt Flag Register – TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR Read/Write Initial Value • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 –...
Page 135 ATmega8535(L) Special Function IO Register – SFIOR ADTS2 ADTS1 ADTS0 – ACME PSR2 PSR10 SFIOR Read/Write Initial Value • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed.
Page 136 Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8535 and peripheral devices or between several AVR devices. Interface – SPI The ATmega8535 SPI includes the following features: • Full Duplex, Three-wire Synchronous Data Transfer •...
Page 137 ATmega8535(L) done, writing a byte to the SPI Data Register starts the SPI Clock Generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener- ator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
Page 138 Table 56. SPI Pin Overrides Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined User Defined Input User Defined Input Note: 1. See “Alternate Functions Of Port B” on page 60 for a detailed description of how to define the direction of the user defined SPI pins.
Page 139 ATmega8535(L) SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPI_MasterTransmit: ; Start transmission of data (r16) SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit C Code Example void SPI_MasterInit(void) /* Set MOSI and SCK output, all others input */...
Page 140 The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) DDR_SPI,r17 ; Enable SPI r17,(1<<SPE) SPCR,r17 SPI_SlaveReceive: ;...
Page 141 ATmega8535(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user.
Page 142 be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
Page 143 ATmega8535(L) SPI Status Register – SPSR SPIF WCOL – – – – – SPI2X SPSR Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled.
Page 144 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo- site edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
Page 145 ATmega8535(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation •...
Page 146 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The clock generation logic consists of synchronization logic for exter- nal clock input used by synchronous slave operation, and the baud rate generator.
Page 147 ATmega8535(L) Figure 70. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter txclk DDR_XCK Sync Edge Register Detector xcki UMSEL xcko DDR_XCK UCPOL rxclk Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal).
Page 148 Table 61. Equations for Calculating Baud Rate Register Setting Equation for Calculating Equation for Calculating Operating Mode Baud Rate UBRR Value Asynchronous Normal Mode -------------------------------------- - ----------------------- - 1 – (U2X = 0) BAUD UBRR 16 UBRR 16BAUD Asynchronous Double Speed ------------------- - 1 Mode (U2X = 1) BAUD...
Page 149 ATmega8535(L) Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed.
Page 150 Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Page 151 ATmega8535(L) The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
Page 152 Data Transmission – The The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the USART Transmitter UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output.
Page 153 ATmega8535(L) Sending Frames with 9 Data If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in Bits UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters.
Page 154 interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
Page 155 ATmega8535(L) Data Reception – The The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the USART Receiver UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input.
Page 156 Receiving Frames with 9 Data If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in Bits UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR, and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.
Page 157 ATmega8535(L) Note: 1. See “About Code Examples” on page 7. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and The USART Receiver has one flag that indicates the receiver state.
Page 158 stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a Parity Error. The PE bit is set if the next character that can be read from the receive buffer had a par- ity error when received and the parity checking was enabled at that point (UPM1 = 1).
Page 159 ATmega8535(L) Figure 73. Start Bit Sampling IDLE START BIT 0 Sample (U2X = 0) Sample (U2X = 1) When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam- ple as shown in the figure.
Page 160 Figure 75. Stop Bit Sampling and Next Start Bit Sampling STOP 1 Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.
Page 161 ATmega8535(L) Table 62. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) Max Total Recommended Max # (Data+Parity Bit) Error (%) Receiver Error (%) slow fast 93.20 106.67 +6.67/-6.8 ± 3.0 94.12 105.79 +5.79/-5.88 ± 2.5 94.81 105.11 +5.11 -5.19...
Page 162 Multi-processor Setting the Multi-processor Communication Mode (MPCM) bit in UCSRA enables a fil- Communication Mode tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
Page 163 ATmega8535(L) Accessing The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore UBRRH/UCSRC some special consideration must be taken when accessing this I/O location. Registers Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written.
Page 164 Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents.
Page 165 ATmega8535(L) For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set.
Page 166 • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec- tively doubling the transfer rate for asynchronous communication.
Page 167 ATmega8535(L) TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. USART Control and Status Register C – UCSRC URSEL UMSEL UPM1...
Page 168 • Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and com- pare it to the UPM0 setting.
Page 169 ATmega8535(L) This bit is used for Synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 68. UCPOL Bit Settings Transmitted Data Changed Received Data Sampled UCPOL...
Page 170 Examples of Baud Rate For standard crystal and resonator frequencies, the most commonly used baud rates for Setting asynchronous operation can be generated by using the UBRR settings in Table 69. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
Page 171 ATmega8535(L) Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) = 3.6864 MHz = 4.0000 MHz = 7.3728 MHz Baud U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1 Rate (bps) UBRR...
Page 172 Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) 11.0592 = 8.0000 MHz = 14.7456 MHz Baud U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR...
Page 173 ATmega8535(L) Table 72. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) = 16.0000 MHz = 18.4320 MHz = 20.0000 MHz Baud U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1 Rate (bps) UBRR...
Page 174 Two-wire Serial Interface Features • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows up to 128 Different Slave Addresses •...
Page 175 ATmega8535(L) Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the opera- tion of the interface.
Page 176 Figure 78. START, REPEATED START, and STOP Conditions START STOP START REPEATED START STOP Address Packet Format All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be per- formed.
Page 177 ATmega8535(L) Figure 80. Data Packet Format Data MSB Data LSB Aggregate SDA From Transmitter SDA From Receiver SCL From Master STOP, REPEATED SLA+R/W Data Byte START or Next Data Byte Combining Address and Data A transmission basically consists of a START condition, a SLA+R/W, one or more data Packets into a Transmission packets and a STOP condition.
Page 178 period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively.
Page 179 ATmega8535(L) Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Page 180 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres- caler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency.
Page 181 ATmega8535(L) • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own Slave address or general call. •...
Page 182 By writing the TWEA bit to zero, the device can be virtually disconnected from the Two- wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus.
Page 183 ATmega8535(L) TWI Status Register – TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR Read/Write Initial Value • Bits 7..3 – TWS: TWI Status These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The dif- ferent status codes are described later in this section.
Page 184 Read/Write Initial Value The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters.
Page 185 ATmega8535(L) Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
Page 186 load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written.
Page 187 ATmega8535(L) In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. Assembly Code Example C Example Comments r16, (1<<TWINT)|(1<<TWSTA)| TWCR = (1<<TWINT)|(1<<TWSTA)| Send START condition.
Page 188 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST), and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM.
Page 189 ATmega8535(L) Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 86). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered.
Page 190 This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is gen- erated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA...
Page 191 ATmega8535(L) Figure 87. Formats and States in the Master Transmitter Mode Successfull DATA transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave Other master Other master...
Page 192 Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 88). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered.
Page 193 ATmega8535(L) A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
Page 194 Figure 89. Formats and States in the Master Receiver Mode Successfull DATA DATA reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave Other master Other master A or A address or data byte continues...
Page 195 ATmega8535(L) To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Value Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master.
Page 196 Table 77. Status Codes for Slave Receiver Mode Status Code Application Software Response (TWSR) To TWCR Prescaler Bits Status of the Two-wire Serial Bus To/from TWDR TWINT TWEA are 0 and Two-wire Serial Interface Next Action Taken by TWI Hardware Hardware 0x60 Own SLA+W has been received;...
Page 197 ATmega8535(L) Figure 91. Formats and States in the Slave Receiver Mode Reception of the own DATA DATA P or S slave address and one or more data bytes. All are acknowledged Last data byte received P or S is not acknowledged Arbitration lost as master and addressed as slave Reception of the general call...
Page 198 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 92.
Page 199 ATmega8535(L) by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source.
Page 200 Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own DATA DATA P or S slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. All 1's P or S Switched to not addressed slave (TWEA = '0')
Page 201 ATmega8535(L) Combining Several TWI In some cases, several TWI modes must be combined in order to complete the desired Modes action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2.
Page 202 Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. •...
Page 203 ATmega8535(L) Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function.
Page 204 ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator.
Page 205 ATmega8535(L) Analog Comparator It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana- Multiplexed Input log Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Ana- log Comparator, as shown in Table 81.
Page 206 Analog-to-Digital Converter Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 65 - 260 µs Conversion Time • Up to 15 kSPS at Maximum Resolution • 8 Multiplexed Single Ended Input Channels • 7 Differential Input Channels •...
Page 207 ATmega8535(L) Figure 98. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 8-BIT DATA BUS ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT MUX DECODER PRESCALER CONVERSION LOGIC AVCC INTERNAL 2.56V REFERENCE SAMPLE &...
Page 208 The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage refer- ence and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
Page 209 ATmega8535(L) Figure 99. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF ADATE SOURCE 1 CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Run- ning mode, constantly sampling and updating the ADC Data Register.
Page 210 The ADC module contains a prescaler, which generates an acceptable ADC clock fre- quency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA.
Page 211 ATmega8535(L) Figure 102. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion MUX and REFS MUX and REFS Complete Update Update Figure 103. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number...
Page 212 Table 82. ADC Conversion Time Sample & Hold (Cycles Conversion Time Condition from Start of Conversion) (Cycles) First conversion 14.5 Normal conversions, single ended Auto Triggered conversions 13.5 Normal conversions, differential 1.5/2.5 13/14 Note: 1. Depending on the state of CK ADC2 Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be...
Page 213 ATmega8535(L) If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1.
Page 214 If differential channels are used, the selected reference should not be closer to AVCC than indicated in Table 114 on page 263 and Table 115 on page 264. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals.
Page 215 ATmega8535(L) Figure 105. Analog Input Circuitry ADCn 1..100 kΩ = 14 pF Analog Noise Canceling Digital circuitry inside and outside the device generates EMI which might affect the Techniques accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1.
Page 216 Offset Compensation The gain stage has a built-in offset cancellation circuitry that nulls the offset of differen- Schemes tial measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results.
Page 217 ATmega8535(L) • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 109. Integral Non-linearity (INL) Output Code Ideal ADC Actual ADC Input Voltage...
Page 218 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is ⋅ 1024 -------------------------- where V is the voltage on the selected input pin and V the selected voltage refer- ence (see Table 84 on page 219 and Table 85 on page 220).
Page 219 ATmega8535(L) Table 83. Correlation Between Input Voltage and Output Codes Read Code Corresponding Decimal Value ADCn /GAIN 0x1FF ADCm + (511/512) V /GAIN 0x1FF ADCm + (510/512) V /GAIN 0x1FE ADCm + (1/512) V /GAIN 0x001 ADCm 0x000 ADCm - (1/512) V /GAIN 0x3FF ADCm...
Page 220 • Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 85 for details.
Page 221 ATmega8535(L) Table 85. Input Channel and Gain Selections (Continued) MUX4..0 Single Ended Input Pos Differential Input Neg Differential Input Gain 11101 ADC5 ADC2 11110 1.22V (V 11111 0V (GND) ADC Control and Status Register A – ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2...
Page 222 Table 86. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor The ADC Data Register – ADCL and ADCH ADLAR = 0 – – – – – – ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value ADLAR = 1 ADC9...
Page 223 ATmega8535(L) Special Function IO Register – SFIOR ADTS2 ADTS1 ADTS0 – ACME PSR2 PSR10 SFIOR Read/Write Initial Value • Bit 7:5 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion.
Page 224 Boot Loader Support The Boot Loader Support provides a real Read-While-Write Self-Programming mecha- nism for downloading and uploading program code by the MCU itself. This feature – Read-While-Write allows flexible application software updates controlled by the MCU using a Flash-resi- Self-Programming dent Boot Loader program.
Page 225 ATmega8535(L) Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write Sec- tion” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Page 226: Boot Loader Lock Bits
Figure 113. Memory sections Program Memory Program Memory BOOTSZ = '10' BOOTSZ = '11' $0000 $0000 Application Flash Section Application Flash Section End RWW End RWW Start NRWW Start NRWW Application Flash Section Application Flash Section End Application End Application Start Boot Loader Boot Loader Flash Section Start Boot Loader...
Page 227 ATmega8535(L) Table 89. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Protection No restrictions for SPM or LPM accessing the Application section. SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Page 228 Store Program Memory The Store Program Memory Control Register contains the control bits needed to control Control Register – SPMCR the Boot Loader operations. SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR Read/Write Initial Value • Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled.
Page 229 ATmega8535(L) the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.
Page 230 Figure 114. Addressing the Flash during SPM ZPCMSB ZPAGEMSB Z - REGISTER PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Notes: 1. The different variables used+ in Figure 114 are listed in Table 95 on page 236. 2.
Page 231 ATmega8535(L) Performing Page Erase by To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
Page 232 Setting the Boot Loader Lock To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to Bits by SPM SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
Page 233 ATmega8535(L) Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. Preventing Flash Corruption During periods of low V the Flash program can be corrupted because the supply volt- age is too low for the CPU and the Flash to operate properly.
Page 234 ; re-enable the RWW section spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcall Do_spm ; transfer data from RAM to Flash page buffer looplo, low(PAGESIZEB) ;init loop variable loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: r0, Y+ r1, Y+ spmcrval, (1<<SPMEN) rcall Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256...
Page 235 ATmega8535(L) temp2, SREG ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence SPMCR, spmcrval ; restore SREG (to enable interrupts if originally enabled) SREG, temp2 ATmega8535 Boot Loader In Table 93 through Table 95, the parameters used in the description of the self pro- Parameters gramming are given.
Page 236 Table 95. Explanation of Different Variables used in Figure 114 and the Mapping to the Z-pointer Corresponding Variable Z-value Description Most significant bit in the Program Counter. PCMSB (The Program Counter is 12 bits PC[11:0]) Most significant bit which is used to address PAGEMSB the words within one page (64 words in a page requires five bits PC [4:0]).
Page 237 ATmega8535(L) Memory Programming Program And Data The ATmega8535 provides six Lock bits which can be left unprogrammed (“1”) or can Memory Lock Bits be programmed (“0”) to obtain the additional features listed in Table 97. The Lock bits can only be erased to “1” with the Chip Erase command. Table 96.
Page 238: Fuse Bits
Table 97. Lock Bit Protection Modes (Continued) Memory Lock Bits Protection Type No restrictions for SPM or LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
Page 239 Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both Serial and Parallel mode, also when the device is locked.
Page 240 Parallel Programming This section describes how to parallel program and verify Flash Program memory, Parameters, Pin EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega8535. Pulses are assumed to be at least 250 ns unless otherwise noted. Mapping, and Commands Signal Names...
Page 241 ATmega8535(L) Table 101. Pin Values Used to Enter Programming Mode Symbol Value PAGEL Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Table 102. XA1 and XA0 Coding Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1) Load Data (High or Low data byte for Flash determined by BS1) Load Command No Action, Idle...
Page 242: Parallel Programming
Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.5V between V and GND, and wait at least 100 µs. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3.
Page 243 ATmega8535(L) Programming the Flash The Flash is organized in pages, see Table 104 on page 241. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to pro- gram the entire Flash memory: A.
Page 244 3. Wait until RDY/BSY goes high. (See Figure 117 for signal waveforms) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2.
Page 245 ATmega8535(L) Programming the EEPROM The EEPROM is organized in pages, see Table 105 on page 241. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash”...
Page 246 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 243 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
Page 247 ATmega8535(L) Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 243 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. 3.
Page 248 Parallel Programming Figure 121. Parallel Programming Timing, Including some General Timing Characteristics Requirements XLWL XHXL XTAL1 DVXH XLDX Data & Contol (DATA, XA0/1, BS1, BS2) PLBX BVPH BVWL WLBX PAGEL PHPL WLWH PLWL WLRL RDY/BSY WLRH Figure 122. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS LOAD DATA...
Page 249 ATmega8535(L) Figure 123. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLOL XTAL1 BVDV OLDV OHDZ ADDR1 (low byte) DATA ADDR0 (low byte) DATA (low byte) DATA (high byte)
Page 250 Table 106. Parallel Programming Characteristics, V = 5V ± 10% Symbol Parameter Units Programming Enable Voltage 11.5 12.5 μA Programming Enable Current Data and Control Valid before XTAL1 High DVXH XTAL1 Low to XTAL1 High XLXH XTAL1 Pulse Width High XHXL Data and Control Hold after XTAL1 Low XLDX...
Page 251 ATmega8535(L) Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed.
Page 252 Serial Programming When writing serial data to the ATmega8535, data is clocked on the rising edge of SCK. Algorithm When reading data from the ATmega8535, data is clocked on the falling edge of SCK. See Figure 125 for timing details. To program and verify the ATmega8535 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 109): 1.
Page 253 ATmega8535(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to deter- mine when the next byte can be written.
Page 254 Table 109. Serial Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Format Instruction Byte 1 Byte 2...
Page 255: Electrical Characteristics
ATmega8535(L) Electrical Characteristics Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Operating Temperature........-55°C to +125°C Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and Storage Temperature ........-65°C to +150°C functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the...
Page 256 = -40°C to 85°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Units Active 4 MHz, V = 3V ATmega8535 Active 8 MHz, V = 5V ATmega8535 Power Supply Current Idle 4 MHz, V = 3V ATmega8535 Idle 8 MHz, V = 5V...
Page 257 ATmega8535(L) If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum V for Power-down is 2.5V. 2502K–AVR–10/06...
Page 258: External Clock Drive Waveforms
External Clock Drive Figure 126. External Clock Drive Waveforms Waveforms External Clock Drive Table 110. External Clock Drive = 2.7V to = 4.5V to Symbol Parameter Units Oscillator Frequency CLCL Clock Period 62.5 CLCL High Time CHCX Low Time CLCX μs Rise Time CLCH...
Page 259: Two-Wire Serial Interface Characteristics
ATmega8535(L) Two-wire Serial Interface Characteristics Table 112 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8535 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 127. Table 112. Two-wire Serial Bus Requirements Symbol Parameter Condition...
Page 260 4. f = CPU clock frequency. 5. This requirement applies to all ATmega8535 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general f requirement. 6. The actual low period generated by the ATmega8535 Two-wire Serial Interface is (1/f - 2/f ), thus f must be greater...
Page 261: Spi Timing Characteristics
ATmega8535(L) SPI Timing See Figure 128 and Figure 129 for details. Characteristics Table 113. SPI Timing Parameters Description Mode SCK period Master See Table 59 SCK high/low Master 50% duty cycle Rise/Fall time Master Setup Master Hold Master Out to SCK Master 5 •...
Page 262 Figure 128. SPI Interface Timing Requirements (Master Mode) (CPOL = 0) (CPOL = 1) MISO (Data Input) MOSI (Data Output) Figure 129. SPI Interface Timing Requirements (Slave Mode) (CPOL = 0) (CPOL = 1) MOSI (Data Input) MISO (Data Output) ATmega8535(L) 2502K–AVR–10/06...
Page 263: Adc Characteristics
ATmega8535(L) ADC Characteristics Table 114. ADC Characteristics, Single Ended Channels Symbol Parameter Condition Units Resolution Single Ended Conversion Bits Single Ended Conversion = 4V, V = 4V ADC clock = 200 kHz Single Ended Conversion = 4V, V = 4V ADC clock = 1 MHz Absolute Accuracy Single Ended Conversion...
Page 264 Table 115. ADC Characteristics, Differential Channels Symbol Parameter Condition Units Gain = Bits Resolution Gain = 10x Bits Gain = 200x Bits Gain = 1x = 4V, V = 5V ADC clock = 50 - 200 kHz Gain = 10x Absolute Accuracy = 4V, V = 5V...
Page 265 ATmega8535(L) Table 115. ADC Characteristics, Differential Channels (Continued) Symbol Parameter Condition Units Internal Voltage Reference 2.56 Reference Input Resistance kΩ Analog Input Resistance MΩ Notes: 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V. 2502K–AVR–10/06...
Page 266 ATmega8535 Typical The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins Characteristics configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source.
Page 267 ATmega8535(L) Figure 131. Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 16 MHz 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 132. Active Supply Current vs. V (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
Page 268 Figure 133. Active Supply Current vs. V (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz °C °C °C Figure 134. Active Supply Current vs. V (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 2 MHz -40°C 25°C...
Page 269 ATmega8535(L) Figure 135. Active Supply Current vs. V (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz °C °C °C Figure 136. Active Supply Current vs. V (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 0.08 0.07...
Page 270 Idle Supply Current Figure 137. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 138. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs.
Page 271 ATmega8535(L) Figure 139. Idle Supply Current vs. V (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz °C °C °C Figure 140. Idle Supply Current vs. V (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz °C °C...
Page 272 Figure 141. Idle Supply Current vs. V (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 2 MHz °C °C °C Figure 142. Idle Supply Current vs. V (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz °C °C...
Page 273 ATmega8535(L) Figure 143. Idle Supply Current vs. V (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL OSCILLATOR 0.04 °C 0.035 0.03 0.025 0.02 0.015 0.01 0.005 Power-Down Supply Current Figure 144. Power-Down Supply Current vs. V (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs.
Page 274 Figure 145. Power-Down Supply Current vs. V (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 0.025 0.02 °C °C °C 0.015 0.01 0.005 Power-Save Supply Current Figure 146. Power-Save Supply Current vs. V (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED °C ATmega8535(L)
Page 275 ATmega8535(L) Standby Supply Current Figure 147. Standby Supply Current vs. V (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 455 kHz RESONATOR, WATCHDOG TIMER DISABLED Figure 148. Standby Supply Current vs. V (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs.
Page 276 Figure 149. Standby Supply Current vs. V (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 2 MHz RESONATOR, WATCHDOG TIMER DISABLED Figure 150. Standby Supply Current vs. V (2 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 2 MHz XTAL, WATCHDOG TIMER DISABLED ATmega8535(L) 2502K–AVR–10/06...
Page 277 ATmega8535(L) Figure 151. Standby Supply Current vs. V (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 4 MHz RESONATOR, WATCHDOG TIMER DISABLED Figure 152. Standby Supply Current vs. V (4 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 4 MHz XTAL, WATCHDOG TIMER DISABLED 2502K–AVR–10/06...
Page 278 Figure 153. Standby Supply Current vs. V (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 6 MHz RESONATOR, WATCHDOG TIMER DISABLED Figure 154. Standby Supply Current vs. V (6 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V 6 MHz XTAL, WATCHDOG TIMER DISABLED ATmega8535(L) 2502K–AVR–10/06...
Page 279 ATmega8535(L) Pin Pullup Figure 155. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V °C °C °C Figure 156. I/O Pin Pull-up Resistor Current vs. Input Voltage (V = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Page 280 Figure 157. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V °C °C °C RESET Figure 158. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V = 2.7V) RESET PULL-UP RESISTOR CURRENT vs.
Page 281 ATmega8535(L) Pin Driver Strength Figure 159. I/O Pin Source Current vs. Output Voltage (V = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V °C °C °C Figure 160. I/O Pin Source Current vs. Output Voltage (V = 2.7V) I/O PIN SOURCE CURRENT vs.
Page 282 Figure 161. I/O Pin Sink Current vs. Output Voltage (V = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V °C °C °C Figure 162. I/O Pin Sink Current vs. Output Voltage (V = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V -40 °C 25 °C...
Page 283 ATmega8535(L) Pin Thresholds And Figure 163. I/O Pin Input Threshold Voltage vs. V , I/O Pin Read As '1') Hysteresis I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' °C °C °C Figure 164. I/O Pin Input Threshold Voltage vs. V , I/O Pin Read As '0') I/O PIN INPUT THRESHOLD VOLTAGE vs.
Page 284 Figure 165. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V °C °C °C Figure 166. Reset Input Threshold Voltage vs. V , Reset Pin Read As '1') RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' °C °C °C...
Page 285 ATmega8535(L) Figure 167. Reset Input Threshold Voltage vs. V , Reset Pin Read As '0') RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' °C °C °C Figure 168. Reset Input Pin Hysteresis vs. V RESET INPUT PIN HYSTERESIS vs. V °C °C °C...
Page 286 BOD Thresholds And Analog Figure 169. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Comparator Offset BOD THRESHOLDS vs. TEMPERATURE BOD LEVEL IS 4.0 V Rising V 3.95 3.85 Falling V 3.75 Temperature (C) Figure 170. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs.
Page 287 ATmega8535(L) Figure 171. Bandgap Voltage vs. V BANDGAP vs. V 1.226 -40°C 1.224 25°C 85°C 1.222 1.22 1.218 1.216 1.214 1.212 1.21 1.208 Vcc (V) Figure 172. Analog Comparator Offset Voltage vs. Common Mode Voltage (V = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 0.002 0.001...
Page 288 Figure 173. Analog Comparator Offset Voltage vs. Common Mode Voltage (V 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 2.7V 0.002 0.001 -0.001 25°C -0.002 85°C -0.003 -40°C -0.004 Common Mode Voltage (V) Internal Oscillator Speed Figure 174. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs.
Page 289 ATmega8535(L) Figure 175. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5V 4.0V 2.7V Temp (C˚) Figure 176. Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V °C °C °C...
Page 290 Figure 177. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs.OSCCAL VALUE 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 178. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs.
Page 291 ATmega8535(L) Figure 179. Calibrated 4 MHz RC Oscillator Frequency vs. V CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. V °C °C °C Figure 180. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 128 144 160 176 192 208 224 240 OSCCAL VALUE 2502K–AVR–10/06...
Page 292 Figure 181. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.05 5.5V 1.95 4.0V 1.85 2.7V 1.75 Temp (C˚) Figure 182. Calibrated 2 MHz RC Oscillator Frequency vs. V CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. V 2.15 °C 2.05...
Page 293 ATmega8535(L) Figure 183. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 184. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs.
Page 294 Figure 185. Calibrated 1 MHz RC Oscillator Frequency vs. V CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. V 1.05 °C 1.03 °C 1.01 °C 0.99 0.97 0.95 0.93 0.91 0.89 0.87 0.85 Figure 186. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs.
Page 295 ATmega8535(L) Current Consumption Of Figure 187. Brownout Detector Current vs. V Peripheral Units BROWNOUT DETECTOR CURRENT vs. V 0.025 °C 0.02 °C °C 0.015 0.01 0.005 Figure 188. ADC Current vs. V (AREF = AVCC) ADC CURRENT vs. V AREF = AVCC °C °C °C...
Page 296 Figure 189. AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. V °C °C °C Figure 190. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V °C °C °C ATmega8535(L) 2502K–AVR–10/06...
Page 297 ATmega8535(L) Figure 191. Programming Current vs. V PROGRAMMING CURRENT vs. V °C °C °C Current Consumption In Figure 192. Reset Supply Current vs. V (0.1 - 1.0 MHz, Excluding Current Through Reset And Reset Pulsewidth The Reset Pull-up) RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5V 5.0V...
Page 298 Figure 193. Reset Supply Current vs. V (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. V 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V Frequency (MHz) Figure 194.
Page 299 ATmega8535(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG 0x3E (0x5E) – – – – – – 0x3D (0x5D) Timer/Counter0 Output Compare Register 0x3C (0x5C) OCR0 0x3B (0x5B) GICR...
Page 300 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2.
Page 301: Instruction Set Summary
ATmega8535(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd ← Rd + Rr Rd, Rr Add two Registers Z,C,N,V,H Rd ← Rd + Rr + C Rd, Rr Add with Carry two Registers Z,C,N,V,H Rdh:Rdl ←...
Page 302 Mnemonics Operands Description Operation Flags #Clocks Rd ← Rr Rd, Rr Move Between Registers None Rd+1:Rd ← Rr+1:Rr MOVW Rd, Rr Copy Register Word None Rd ← K Rd, K Load Immediate None Rd ← (X) Rd, X Load Indirect None Rd ←...
Page 303 ATmega8535(L) Mnemonics Operands Description Operation Flags #Clocks SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/Timer) None BREAK Break For On-chip Debug Only None 2502K–AVR–10/06...
Page 304: Ordering Information
44M1 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive).Also Halide free and fully Green.
Page 305 ATmega8535(L) Package Type 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44M1-A 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2502K–AVR–10/06...
Page 306 Packaging Information PIN 1 PIN 1 IDENTIFIER 0˚~7˚ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL NOTE – – 1.20 0.05 – 0.15 0.95 1.00 1.05 11.75 12.00 12.25 9.90 10.00 10.10 Note 2 11.75 12.00 12.25 Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 9.90 10.00 10.10...
Page 307 ATmega8535(L) 40P6 SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) 0º ~ 15º NOTE SYMBOL – – 4.826 0.381 – – 52.070 – 52.578 Note 2 15.240 – 15.875 13.462 – 13.970 Note 2 0.356 – 0.559 1.041 – 1.651 Notes: 1.
Page 308 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) IDENTIFIER 0.191(0.0075) D2/E2 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL NOTE 4.191 – 4.572 2.286 – 3.048 0.508 – – 17.399 – 17.653 16.510 – 16.662 Note 2 17.399...
Page 309 ATmega8535(L) 44M1-A Marked Pin# 1 ID SEATING PLANE TOP VIEW Pin #1 Corner SIDE VIEW Pin #1 Option A Triangle COMMON DIMENSIONS (Unit of Measure = mm) NOTE SYMBOL Option B 0.80 0.90 1.00 Pin #1 Chamfer – 0.02 0.05 (C 0.30) 0.25 REF 0.18...
Page 310 Errata The revision letter refer to the device revision. ATmega8535 • First Analog Comparator conversion may be delayed • Asynchronous Oscillator does not stop in Power-down Rev. A and B 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising V , the first Analog Comparator conver- sion will take longer than expected on some devices.
Page 311 ATmega8535(L) Datasheet Revision Please note that the referring page numbers in this section are referring to this docu- ment. The referring revision in this section are referring to the document revision. History Changes from Rev. 1. Updated TOP/BOTTOM description for all Timer/Counters Fast PWM mode. 2502J- 08/06 to Rev.
Page 312 Changes from Rev. 1. Removed “Advance Information” and some TBD’s from the datasheet. 2502C-04/03 to Rev. 2. Added note to “Pinout ATmega8535” on page 2. 2502D-09/03 3. Updated “Reset Characteristics” on page 37. 4. Updated “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical Characteristics”...
Page 313 ATmega8535(L) 14. Updated “ADC Characteristics” on page 263. 14. Updated “Register Summary” on page 299. 15. Various Timer 1 corrections. 16. Added WD_FUSE period in Table 108 on page 253. Changes from Rev. 1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles. 2502A-06/02 to Rev.
Page 314 ATmega8535(L) 2502K–AVR–10/06...
Page 315 ATmega8535(L) Table of Contents Features....................1 Pin Configurations................2 Disclaimer ......................2 Overview....................3 Block Diagram ...................... 3 AT90S8535 Compatibility ..................4 Pin Descriptions....................5 Resources .................... 6 About Code Examples................. 7 AVR CPU Core ..................8 Introduction ......................8 Architectural Overview..................
Page 316 Standby Mode..................... 34 Extended Standby Mode ..................34 Minimizing Power Consumption ................. 35 System Control and Reset ..............36 Internal Voltage Reference ................. 41 Watchdog Timer ....................41 Timed Sequences for Changing the Configuration of the Watchdog Timer ..45 Interrupts ....................
Page 317 ATmega8535(L) Overview......................117 Timer/Counter Clock Sources................118 Counter Unit...................... 119 Output Compare Unit..................119 Compare Match Output Unit ................121 Modes of Operation ..................122 Timer/Counter Timing Diagrams............... 126 8-bit Timer/Counter Register Description ............128 Asynchronous Operation of the Timer/Counter ..........131 Timer/Counter Prescaler...................
Page 318: Table Of Contents
Prescaling and Conversion Timing ..............209 Changing Channel or Reference Selection ............212 ADC Noise Canceler..................214 ADC Conversion Result..................218 Boot Loader Support – Read-While-Write Self-Programming ..224 Boot Loader Features ..................224 Application and Boot Loader Flash Sections ............ 224 Read-While-Write and No Read-While-Write Flash Sections......
Page 319 ATmega8535(L) Errata ....................310 ATmega8535 Rev. A and B..................... 310 Datasheet Revision History ............311 Changes from Rev. 2502J- 08/06 to Rev. 2502K- 10/06........311 Changes from Rev. 2502I- 06/06 to Rev. 2502J- 08/06 ........311 Changes from Rev. 2502H- 04/06 to Rev. 2502I- 06/06 ........311 Changes from Rev.
Page 320 ATmega8535(L) 2502K–AVR–10/06...
Page 321 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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