Atmel AVR ATmega324PA Specification Sheet

Atmel AVR ATmega324PA Specification Sheet

8-bit microcontroller with 16/32/64/128k bytes in-system programmable flash summary

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Features
High-performance, Low-power AVR
Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 16/32/64/128K Bytes of In-System Self-programmable Flash program memory
(ATmega164PA/324PA/644PA/1284P)
– 512B/1K/2K/4K Bytes EEPROM (ATmega164PA/324PA/644PA/1284P)
– 1/2/4/16K Bytes Internal SRAM (ATmega164PA/324PA/644PA/1284P)
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel, 10-bit ADC
Differential mode with selectable gain at 1x, 10x or 200x
– Byte-oriented Two-wire Serial Interface
– Two Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and
Extended Standby
I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
– 44-pad DRQFN
– 49-ball VFBGA
Operating Voltages
– 1.8 - 5.5V
Speed Grades for ATmega164PA/324PA/644PA/1284P
– 0 - 20MHz @ 1.8 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active: 0.4 mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.6µA (Including 32 kHz RTC)
Note:
1. See
"Data Retention" on page 9
®
8-bit Microcontroller
(1)
for details.
8-bit
Microcontroller
with
16/32/64/128K
Bytes In-System
Programmable
Flash
ATmega164PA
ATmega324PA
ATmega644PA
ATmega1284P
Summary
Rev. 8152GS–AVR–11/09

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Summary of Contents for Atmel AVR ATmega324PA

  • Page 1 – Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32 kHz RTC) Note: 1. See ”Data Retention” on page 9 ® 8-bit Microcontroller for details. 8-bit Microcontroller with 16/32/64/128K Bytes In-System Programmable Flash ATmega164PA ATmega324PA ATmega644PA ATmega1284P Summary Rev. 8152GS–AVR–11/09...
  • Page 2: Pin Configurations

    1. Pin Configurations Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164PA/324PA/644PA/1284P Figure 1-1. Note: 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6...
  • Page 3 Pinout - DRQFN for ATmega164PA/324PA/644PA Figure 1-2. Table 1-1. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P DRQFN - Pinout Top view DRQFN - Pinout RESET XTAL2 XTAL1 Bottom view AVCC AREF...
  • Page 4: Bottom View

    Pinout - VFBGA for ATmega164PA/324PA/644PA Figure 1-3. Table 1-2. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P VFBGA - Pinout Top view BGA - Pinout RESET XTAL2 XTAL1 Bottom view AREF AVCC...
  • Page 5: Block Diagram

    2. Overview The ATmega164PA/324PA/644PA/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164PA/324PA/644PA/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2-1.
  • Page 6 In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
  • Page 7: Pin Descriptions

    Pin Descriptions 2.3.1 Digital supply voltage. 2.3.2 Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.
  • Page 8 2.3.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
  • Page 9: Data Retention

    3. Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
  • Page 10: Register Summary

    6. Register Summary Address Name Bit 7 (0xFF) Reserved (0xFE) Reserved (0xFD) Reserved (0xFC) Reserved (0xFB) Reserved (0xFA) Reserved (0xF9) Reserved (0xF8) Reserved (0xF7) Reserved (0xF6) Reserved (0xF5) Reserved (0xF4) Reserved (0xF3) Reserved (0xF2) Reserved (0xF1) Reserved (0xF0) Reserved (0xEF) Reserved (0xEE) Reserved...
  • Page 11 Address Name Bit 7 (0xC0) UCSR0A RXC0 (0xBF) Reserved (0xBE) Reserved (0xBD) TWAMR TWAM6 (0xBC) TWCR TWINT (0xBB) TWDR (0xBA) TWAR TWA6 (0xB9) TWSR TWS7 (0xB8) TWBR (0xB7) Reserved (0xB6) ASSR (0xB5) Reserved (0xB4) OCR2B (0xB3) OCR2A (0xB2) TCNT2 (0xB1) TCCR2B FOC2A (0xB0)
  • Page 12 Address Name Bit 7 (0x7E) DIDR0 ADC7D (0x7D) Reserved (0x7C) ADMUX REFS1 (0x7B) ADCSRB (0x7A) ADCSRA ADEN (0x79) ADCH (0x78) ADCL (0x77) Reserved (0x76) Reserved (0x75) Reserved (0x74) Reserved (0x73) PCMSK3 PCINT31 (0x72) Reserved (0x71) Reserved (0x70) TIMSK2 (0x6F) TIMSK1 (0x6E) TIMSK0 (0x6D)
  • Page 13 Address Name Bit 7 0x1C (0x3C) EIFR 0x1B (0x3B) PCIFR 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) Reserved 0x17 (0x37) TIFR2 0x16 (0x36) TIFR1 0x15 (0x35) TIFR0 0x14 (0x34) Reserved 0x13 (0x33) Reserved 0x12 (0x32) Reserved 0x11 (0x31) Reserved 0x10 (0x30) Reserved 0x0F (0x2F)
  • Page 14: Instruction Set Summary

    7. Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS Rd, Rr Add two Registers Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register Rd, Rr Subtract with Carry two Registers SBCI...
  • Page 15 Mnemonics Operands BRVC Branch if Overflow Flag is Cleared BRIE Branch if Interrupt Enabled BRID Branch if Interrupt Disabled BIT AND BIT-TEST INSTRUCTIONS Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right SWAP...
  • Page 16 Mnemonics Operands PUSH Push Register on Stack Pop Register from Stack MCU CONTROL INSTRUCTIONS No Operation SLEEP Sleep Watchdog Reset BREAK Break 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P Description STACK ← Rr Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Operation Flags...
  • Page 17: Ordering Information

    1.8 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
  • Page 18 1.8 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
  • Page 19 1.8 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
  • Page 20 1.8 - 5.5V Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
  • Page 21: Packaging Information

    9. Packaging Information PIN 1 0˚~7˚ Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
  • Page 22 40P6 SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P 0º...
  • Page 23 44M1 Marked Pin# 1 ID TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P Pin #1 Corner Pin #1 Option A Triangle Option B Pin #1 Chamfer (C 0.30) Option C...
  • Page 24 44MC Pin 1 ID BOTTOM VIEW 1. The terminal #1 ID is a Laser-marked Feature. Note: Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P TOP VIEW eT/2 0.40 R0.20 TITLE 44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body, 2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package...
  • Page 25 49C2 A1 BALL ID A1 BALL CORNER Package Drawing Contact: packagedrawings@atmel.com 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P TOP VIEW 49 - 0.35 ± 0.05 Ø BOTTOM VIEW TITLE 49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch, 5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) 0.10...
  • Page 26 10. Errata 10.1 ATmega164PA Rev. E No known Errata. 10.2 ATmega324PA Rev. F No known Errata. 10.3 ATmega644PA Rev. F No known Errata. 8152GS–AVR–11/09 ATmega164PA/324PA/644PA/1284P...
  • Page 27: Datasheet Revision History

    11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. 8152G- 11/09 11.2 Rev. 8152F- 10/09 11.3 Rev.
  • Page 28 “ATmega644PA” Ordering Information. Updated ”Errata” on page 430. Updated ”Features” on page 1 by inserting ATmega324PA device and updated the whole datasheet accordingly. Updated ”Overview” on page Inserted ”Comparison Between ATmega164PA and ATmega324PA” on page Updated all resgister description in ”AVR CPU Core”...
  • Page 29 11.7 Rev. 8152A- 11/08 Initial revision (Based on the ATmega164P/324P/644P datasheet 8011K-AVR-09/08). Changes done compared to ATmega164P/324P/644P datasheet 8011K-AVR-09/08: –New graphics in ”Typical Characteristics” on page 337 –New ”Ordering Information” on page 395...
  • Page 30 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...

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