Atmel ATmega8535L User Manual page 8

AVR CPU Core
Introduction
Architectural Overview
ATmega8535(L)
8
This section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Figure 3. Block Diagram of the AVR MCU Architecture
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being exe-
cuted, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-
System Re-Programmable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
8-bit Data Bus
Program Status
Counter and Control
32 x 8
General
Purpose
Registrers
ALU
Data
SRAM
EEPROM
I/O Lines
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
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