SiS5103 System I/O & PMU
•
Integrated bridge between PCI bus and ISA bus.
∗
Translates PCI bus cycles into ISA bus cycles.
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Translates ISA master or DMA cycles into PCI bus cycles.
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Provides PCI-to-ISA memory one Double Word Posted Write Buffer.
•
Integrated ISA bus compatible logic.
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ISA bus controller.
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ISA arbiter for ISA master, DMA devices, and refresh.
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Built-in two 8237 compatible DMA controllers.
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Built-in two 8259A compatible interrupt controllers.
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Built-in one 8254 timer.
•
Supports reroutibility of four PCI interrupts to any unused IRQ interrupt.
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Supports flash ROM.
•
Built-in RTC with 242 bytes extended CMOS SRAM.
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Built-in PCI IDE.
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Fully compatible with PCI local bus specification v2.0.
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Accommodates 8 bits, 16 bits, and 32 bits data transfer.
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Supports PCI burst read/write operation.
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Supports read ahead & posted write buffers for concurrent system operation.
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Controls two IDE channels and max. connects 4 IDE drives.
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Supports PIO mode 4 timing proposal on enhanced IDE specifications.
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Programmable command and recovery timing for reads and writes per channel.
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Auto IDE channel speed setting with software driver.
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Hardware and software chip disable capability.
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Supports power down feature.
•
Meet PCI specification buffer strength.
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Supports CPU thermal detectio n.
•
Supports CPU throttling and clock slow down.
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Supports software SMI and software stop clock port.
•
Supports Microsoft APM spec.
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Supports user register 32-bit.
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External hardware SMI request support.
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EXTSUSP, GPIO[3:0], PIO[6:0], UIP [2:0].
•
Supports four Power Management Mode.
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Local auto doze mode.
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Global auto doze mode.
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Standby mode.
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Suspend mode.
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Supports programmable PMU timer.
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Seven sub-doze timer: 31mS/125mS/05.Sec/1Sec/1.5Sec/2Sec/3Sec.
∗
Standby timer: 4 sec
∗
Suspend time: 1 min
∼
5 min.
∼
60 min.
62
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