Table of Contents
Advertisement
Processor PCB
STATUS REGISTER
7
6
5
4
3
2
I
0 ..
I I I I I I I I I
I
I
I
I
I
I
1
1
I
BIT NUMBER
CHANNEL
0
HAS REACHEDTC
CHANNELIHASREACHEDTC
CHANNEL 2 HAS REACHED TC
CHANNEL3HASREACHEDTC
CHANNEL 0 REQUEST
CHANNEL 1 REQUEST
CHANNEL 2 REQUEST
CHANNEL 3 REQUEST
THIS INFORMATION INCLUDES WHICH CHANNELS HAVE REACHED A TERMINAL COUNT AND WHICH
CHANNELS HAVE A PENDING DMA REQUEST. BITS 0 THROUGH 3 ARE SET EVERY TIME A TC IS REACHED BY
THAT CHANNEL OR AN EXTERNAL EOP IS APPLIED. THESE BITS ARE CLEARED UPON RESET AND ON EACH
STATUS READ.
Figure 2-12 DMA Status Register
2.4
INTERV AL TIMER
The NEC J1PD8253-5 Programmable Interval Timer has three timer counter out-
puts: ChannelO is attached to interrupt-request Channel 3; Channell is sent to the
synchronous/asynchronous communications controller on the Controller PCB (see
Chapter 3); Channel 2 is not used. Figure 2-13 is a block diagram of the interval
timer. Table 2-3 lists the timer commands.
08
TO DIS
2.4576 MHz
Al
A2
lOW
lOR
CS
IRT
RESET
COMM.
8
8253-5
CLKO
CLKI
AO
Al
WR
RD
CS
(LOGIC "1")
X111
r--
LS -
7 - 4
- l - -__ _
TO
t - - - - - - t
CP
FIF
...----0
MR
T1
Figure 2-13 Interval Timer Block Diagram
IRQ3
BUS
2-19
Advertisement
Table of Contents
