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2-14
The 1,048,576 bytes of available memory space are addressed as if divided into
logical segments of up to 64 KB each. The 8086 has direct access to four segments at
a time, each of which has a base address carried in one offour segment registers: the
Code Segment (CS), Data Segment (DS), Stack Segment (SS), and Extra Segment
(ES). The Instruction Pointer (IP) register contains the present offset distance in
bytes, which completes the logical address of the next address to be processed. The
result of this memory organization is that the 20-bit physical memory address can
be defined by a logical address consisting of two 16-bit bytes, the first specifying the
base address of the selected segment and the second specifying the relative address
within that segment, counting from the base address. To convert a logical address to
a physical address, first shift the base address byte 4 bits to the left by multiplying it
by sixteen, then add the result to the offset byte.
2.3
DIRECT MEMORY ACCESS
Because it bypasses processor intervention, DMA provides a much faster way of
moving data between I/O devices and memory. Supported by the NEC LSI 8237-5
DMA Controller, DMA employs 16 address lines and 4 bits of page addressing,
thus enabling it to address one megabyte of memory. Although the DMA is a
synchronous device, it can interface with low-speed memory or I/O devices by using
the external Ready line.
The four DMA channels are assigned as follows:
ChannelO
CRT
Channel 1 FD D
Channel 2
Reserved for graphic operations option
Channel 3
Future.
See Table 2-2 for a list of instructions and I/O addresses. Figures 2-10, 2-11, and
2-12 show the DMA registers.
Table 2-2 DMA Instructions
INSTRUCTION
READ/
110
DATA BUS
WRITE
ADDRESS
7
6
5
4
3
2
1
0
Write Command
W
09
K
D
W
P
T
C
A
M
S
S
S
R
M
E
H
M
M
M
I
A
T
T
C
C
Write Mode
W
IB
S
S
R
R
S
S
1
0
D
T
1
0
1
0
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