Table of Contents
Advertisement
Processor PCB
2-20
Table 2-3 Timer Commands
INSTRUCTION
READ/
I/O
DATA BUS
WRITE
ADDRESS
7
6
5
4
3
2
I
0
Load Counter 0
W
29
C7 C6 C5 C4 C3 C2 CI CO
Cl5 Cl4 Cl3 Cl2 CII ClO C9 C8
Load Counter I
W
2B
C7 C6 C5 C4 C3 C2 CI CO
Cl5 Cl4 Cl3 Cl2 CII ClO C9 C8
S
S
R
R
B
Mode Set
W
2F
C
C
L
L M2 MI MO
C
I
0
I
0
D
Timer Reset
W
46
X
X
X
X X
T
X
X
M
X:
Don't care.
2.5
INTERRUPT CONTROL
This interrupt function is controlled by two 8259 Metal Oxide Semiconductor
(MOS) devices; each can handle up to eight vectored priority interrupts, as shown in
Figure 2-14. The first 8259 device (master) supports IRO through IR6, with IR7
cascaded from the second 8259 device (slave), which supports IR7 through IRI4.
These 15 available interrupt lines are assigned to service specific devices in order of
priority. Table 2-4 lists the interrupt lines.
There are two interactions between the processor and the interrupt controller. The
first is the acknowledgement process, during which the processor transmits
acknowledgement of the interrupt request to the interrupt controller. During the
second process, the interrupt controller transmits a byte of data to the processor
(see Table 2-4).
Control commands issued by the processor, consisting of Initialization Command
Words (ICW) and Operational Command Words (OCW), are summarized in Table
2-5 and shown in Figures 2-15 and 2-16. Table 2-5 also includes poll mode, read
interrupt register (IRR), read inservice register (ISR), and interrupt register words
that are read into the data bus by the interrupt controller when so commanded.
Advertisement
Table of Contents
