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COnTrOller rClJ
3-10
Table 3-3 Contents of the GDC Status Register
BIT
DESCRIPTION
o
When this flag is a' 1', it indicates tha t a byte is available to be read by the
system microprocessor. This bit must be tested before each read opera-
tion. It drops to a '0' while the data is transferred from the FIFO into the
microprocessor interface data register.
1
A' l' at this flag indicates a full FIFO in the GDC. A '0' ensures that there
is room for at least one byte. This flag needs to be checked before each
write into the GDC.
2
This bit and the FIFO-Full flag coordinate system microprocessor
accesses with the GDC FIFO. When the bit is '1', the Empty flag ensures
that the commands and parameters previously sent to the GDC have
been processed.
3
While the GDC is drawing a graphics figure, this status bit is a 'I'.
4
This bit is a '1' during DMA data transfers.
5
Vertical retrace sync occurs while this flag is a 'I'. The vertical sync flag
coordinates display format modifying commands to the blanked interval
surrounding vertical sync. This eliminates display disturbances.
6
A '1' value for this flag signifies that horizontal retrace blanking is
currently underway.
7
Not used.
The FIFO is an internal buffer ofthe GDC that stores microprocessor commands.
Access to the FIFO is coordinated through flags in the status register. The com-
mand processor fetches command bytes from the FIFO and interprets them. The
command bytes are decoded and succeeding parameters are distributed to their
proper destinations within the GDC. The command processor yields to the bus
interface when both access the FIFO simultaneously.
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