Table of Contents
Advertisement
• A l5-channel interrupt controller to govern access to the microprocessor
and data bus
• 8 KB (4K x 16 bits) of ROM, which carry out self-testing and flexible-disk
bootstrap loading.
• 128 KB of RAM organized into sixteen 64K x 1 dynamic-memory chips,
plus two more for parity check
• 4 KB (2K x 16 bits) of CMOS Battery-Backed Memory (BBM)
• Keyboard control logic, which controls and conveys data from the Key-
board to the data bus
• Parallel printer control, which interfaces with a connector on the APC rear
panel for connection of a printer or similar device
• Calendar and clock generator, supported by NEC tJPD1990AC, which is
battery-protected and generates day, month, day of the week, hour, minute,
and second information.
2.1
MOTHER BOARD/CARD CAGE INTERFACE
The Mother Board contains five card-edge socket connectors, each having 100
contacts, 50 on a side (see Figure 2-3). All contacts are connected as a bus to each
PCB socket.
R50 R49
t
FRONT
\\
I
LSO
I
L49
I:::
<>
I
I
I
I
I I:::
LJUu-
Figure 2-3 Mother Board/Card Cage Interface
R2 Rl
II
I
::::11
: : : : 1
I
moOD,
TOP
VIEW
~
LI
L2
Table 2-1 lists the contact assignments for each socket. All signals on these contacts
are Transistor/Transistor Logic (TTL) compatible. Time relationships between
various contacts in the card cage bus are shown in Figures 2-4 through 2-7.
110
equivalent circuits for the affected contacts and devices are shown in Figures 2-8
and 2-9.
Processor PCB
2-3
Advertisement
Table of Contents
