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Processor PCB
2-16
Table 2-2 DMA Instructions (cont'd)
INSTRUCTION
READ/
I/O
DATA BUS
WRITE
ADDRESS
7
6
5
4
3
2
CHO Page Register
W
38
0
0
0
0
A
A
19
18
CH 1 Page Register
W
3A
0
0
0
0
A
A
19
18
CH2 Page Register
W
3C
0
0
0
0
A
.'\
19
18
CH3 Page Register
W
3E
0
0
0
0
A
A
19
18
Read Temp Register
R
ID
D
D
D
D
D
D
7
6
5
4
3
2
Master Clear
W
ID
-
-
-
-
-
-
COMMAND REGISTER
7
6
5
4
3
2
1
0 -
BIT NUMBER
l J 1 I I I I I I
I
o
MEMORY-TO-MEMORY DISABLE
X DON'T CARE
I
(
I
(
o
CONTROLLER ENABLE
1
CONTROLLER DISABLE
o
NORMAL TIMING
o
FIXED PRIORITY
1 ROTATING PRIORITY
o
LATE WRITE SELECTION
o
DREQ SENSE ACTIVE HIGH
o
DACK SENSE ACTIVE LOW
Figure 2-10 DMA Command and Mode Registers
1
0
A
A
17
16
A
A
17
16
A
A
17
16
A
A
17
16
D
D
1
0
-
-
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