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Pin No.
Name
103
RD/WR
104
PTE[7]/PCC0RDY/AUDSYNC
105
CS0
106
CS2
107
CS3
108
CS4/PTK[2]
109
CS5/CE1A/PTK[3]
110
CS6/CE1B
111
CE2A/PTE[4]
112
CE2B/PTE[5]
113
AFE_Hc1/USB1d_Dpls/Ptk[0]
114
AFE_Rly/USB1d_Dmns/Ptk[1]
115
VssQ
116
AFE_SCLK/USB1d_TXDPLS
117
VccQ
118
Ptm7/Pint7/Afe_FS/USB_RCV
119
Ptm6/Pint6/Rxin/USB_Speed
120
Ptm5/Pint5/Txo/USB_Txse0
121
Ptm4/Pint4/Rdet/USB_TxD-
122
Reserve/USB1d_SUSPEND
123
USB1_ovr_crnt/USBF_VBUS
124
USB2_ovr_crnt
125
RTS2/USB1d_TXENL
126
PTE[2]/USB1_pwr_en
127
PTE[1]/USB2_pwr_en
128
CKE/PTK[5]
129
RAS3/PTJ[0]
130
Reserve/PTJ[1]
131
Reserve/CAS/PTJ[2]
132
VssQ
133
Reserve/PTJ[3]
134
VccQ
135
Reserve/PTJ[4]
136
Reserve/PTJ[5]
137
Vss
138
PTD[5]/CL1
139
Vcc
140
PTD[7]/DON
141
PTE[6]/M_DISP
142
PTE[3]/FLM
143
PTE[0]/TDO
144
PCC0RESET/DRAK0
145
PCC0DRV/DACK0
146
WAIT
147
RESETM
148
ADTRG/PTH[5]
149
IOIS16/PTG[7]
150
ASEMD0
151
PTG[5]/ASEBRKAK
152
PTG[4]
153
PCC0BVD2/PTG[3]/AUdata[3]
154
PCC0BVD1/PTG[2]/AUdata[2]
155
Vss
156
PCC0CD2/PTG[1]/AUDATA[1]
157
Vcc
158
PCC0CD1/PTG[0]/AUDATA[0]
159
VssQ
160
PTF[7]/PINT[15]/TRST
161
VccQ
162
PTF[6]/PINT[14]/TMS
163
PTF[5]/PINT[13]/TDI
164
PTF[4]/PINT[12]/TCK
165
PTF[3]/PINT[11]/Reserve
166
PCCREG/PTF[2]/Reserve
167
PCC0VS1/PTF[1]/Reserve
168
PCC0VS2/PTF[0]/Reserve
169
MD0
170
Vcc-PLL1
171
CAP1
Function Name
Function
RDWR
Read / Write
AUDSYNC [for ICE]
AUD_SYNC
CS0
Chip Select_0 Flash Memory [32bit]
CS2
Chip select_2 Peripheral Device_1 [16bit]
CS3
Chip select_3 SDRAM
CS4
Chip select_4 Peripheral Device_2 [8bit]
CS5
Chip select_5 Peripheral Device_3 [32bit]
CS6
Chip select_6
(Reserve)
Area_5 PCMCIA Card Enable / I/O Port_E
(Reserve)
Area_6 PCMCIA Card Enable / I/O Port_E
AFE Hardware Control / D+ Input / I/O Port_K
AFE Relay Control / D- Input / I/O Port_K
GND
Vss for I/O (0V)
AFE Clock / D+ Output
3.3V
Vcc for I/O (3.3V)
Port_M / Port Interrupt / AFE Frame Sync / Receiver
Port_M / Port Interrupt / AFE Receiver / Speed Control
Port_M / Port Interrupt / AFE Transceiver / SE0 State
Port_M / Port Interrupt / AFE Ringing Det/ D- Out
Reserve / Transceiver Suspend Status
(USBF_VBUS)
USB Function VBUS
(USB2_ovr_crnt)
USB Host_2 Over Current Detector
(USB Digital)
SCIF RTS / USB Output Enable
(USB1_pwr_en)
USB1 Power Control
(USB2_pwr_en)
USB2 Power Control
CKE
CK Enable (SDRAM)
RAS3
RAS for SDRAM
PW_FLASH
Reserve / I/O Port_J
CAS
CAS for SDRAM
GND
Vss for I/O (0V)
POWER_SW2
Power SW for BGA Board
3.3V
Vcc for I/O (3.3V)
SCLK_GAM
Serial Clock Output
SDATA_GAM
Serial Data Output
GND
Vss (0V)
RESET_PW
PIXEL Reset Signal
1.9V
Vcc (1.9V)
PW_SEL
PIXEL 232CSelect
EXP_RESET
EXPANDER Reset Signal
USB_RESET
USB Reset Signal
TDO [for ICE]
Test Data Output
WAIT
FPGA2 Hardware Wait
RESETM
Manual Reset
(Reserve)
Analog Trigger / Port_H
ASEMD0 [ICE]
ASE Mode
ASEBRKAK [ICE]
ASE Break Acknowledge
AUDATA[3] [ICE]
AUD Data
AUDATA[2] [ICE]
AUD Data
GND
Vss (0V)
AUDATA[1] [ICE]
AUD Data
1.9V
Vcc (1.9V)
AUDATA[0] [ICE]
AUD Data
GND
Vss for I/O (0V)
TRST [ICE]
Test Reset
3.3V
Vcc for I/O (3.3V)
TMS [ICE]
Test Mode SW
TDI [ICE]
Test Data Input
TCK [ICE]
Test Clock
PCCREG / Port_F / Reserve
PCCVS1 / Port_F / Reserve
PCCVS2 / Port_F / Reserve
MD0
Clock Mode Setting [Default:L]
1.9V
Vcc for PLL1 (1.9V)
CAP1
Capacitor for PLL1[470pF]
-99-
Control Port Functions
Polarity
[32bit]
(Open)
(Open)
(Open)
(Open)
-
(Pull-up)
-
(Open)
(Open)
(Open)
(Open)
(Open)
(Open)
(Open)
-
(L= Off / H= On)
-
-
-
-
-
-
(H: SH, L: PW)
-
-
-
(Open)
(Open)
-
-
-
(Open)
-
-
(Open)
-
-
-
-
-
-
-
-
-
-
-
-
(Open)
(Open)
(Open)
(Open)
-
-
-
I/O
O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
I
I
O
O
O
O
O
-
O
-
O
O
-
O
-
O
O
O
O
-
-
I
I
-
-
I
O
-
O
O
-
O
-
O
-
I
-
I
I
I
-
-
-
I
-
-
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