Sony HXCU-100 Service Manual page 227

from DEMUX FPGA +3.2V
017 RTP_OUT
+5V-D
IC1800
NJM2871BF33-TE2
CL1800
R1826
0.8
47 FB1800
5 4
VIN VOUT
R1800 C1802
2.2k
1 3 1uF
CTL N_BYP 6.3V
GND
C1800 C1801
C1808 from POST FPGA
0.1uF 0.1uF
1uF 2
6.3V 10V 10V
from POST FPGA
GND
R1829
100
004,009 DAY_PLL33_P-ON-p
HXCU-100
A B
DPR-300 (18/28)
R1806
DAYTONA-MAIN-H R1807
DAYTONA-MAIN-C9
DAYTONA-MAIN-C7
RB1804
DAYTONA-MAIN-C5
22
DAYTONA-MAIN-C3
DAYTONA-MAIN-C1
RB1805
DAYTONA-MAIN-Y9
22
DAYTONA-MAIN-Y7
DAYTONA-MAIN-Y5
DAYTONA-MAIN-Y3
RB1806
DAYTONA-MAIN-Y1
22
DAYTONA-MAIN-GPIO_1 R1801
+2.5V
+3.3V_PLL_DEC
+3.2V
020 DAYTONA-MAIN-FRSEL
R1802
020 DAYTONA-MAIN-FFWRT
R1803
+3.2V
R1804
020 DAYTONA-MAIN-F-RESET
R1810
DAYTONA-MAIN-UART-RX
020
7
RTP-DT31
RB1800 5
RTP-DT29
47
RTP-DT27 3
1
RTP-DT25
RTP-DT23 7
RB1801 5
RTP-DT21
47
RTP-DT19 3
1
RTP-DT17
RTP-DT15 7
RB1802 5
RTP-DT13
47
3
RTP-DT11
RTP-DT9 1
RTP-DT7 7
RB1803
RTP-DT5 5
47
3
RTP-DT3
RTP-DT1 1
R1808
RTP-EN
RTP-STA R1809
C
DPR-300 (18/28)
DAYTONA-MAIN-F
DY-23
MAIN(DEC)
CL1801
CN1800
1.2
(Reserve) 2 1 MCLC_VAL_DE
R1816
22
MCLC_VAL_V 4 3 MCLC_FLD
22
MCLC_VAL_H 6 5 MCLC_CK
GND 8 7 GND
2 1 2
MCLC_C(11) 10 9 MCLC_C(10)
4 3 4
MCLC_C(9) 12 11 MCLC_C(8)
RB1811
6 5 6
MCLC_C(7) 14 13 MCLC_C(6)
22
8 7 8
MCLC_C(5) 16 15 MCLC_C(4)
2 1 2
MCLC_C(3) 18 17 MCLC_C(2)
4 3 4
MCLC_C(1) 20 19 MCLC_C(0)
RB1812
6 5 6
GND 22 21 GND
22
8 7 8
MCLC_Y(11) 24 23 MCLC_Y(10)
MCLC_Y(9) 26 25 MCLC_Y(8)
2 1 2
MCLC_Y(7) 28 27 MCLC_Y(6)
4 3 4
MCLC_Y(5) 30 29 MCLC_Y(4)
RB1813
6 5 6
MCLC_Y(3) 32 31 MCLC_Y(2)
22
8 7 8
MCLC_Y(1) 34 33 MCLC_Y(0)
GND 36 35 GND
220 R1814
GPIO(1) 38 37 GPIO(0)
GND 40 39 +2.5V
C1806
GND 42 41 +2.5V
GND 44 43 +1.2V
GND 46 45 +1.2V
GND 48 47 +1.2V
FB1801 GND 50 49 +1.2V
C1804
+V_RG18 52 51 GND 10uF
+V_RG18 54 53 GND
+3.3V_PLL_DEC
+V_RG18 56 55 GND
+3.3V_PLL 58 57 +3.3V_PLL
C1809 GND 60 59 +3.3V
10uF
GND 62 61 +3.3V
GND 64 63 +3.3V
C1805 10uF
GND 66 65 +3.3V
220
FRSEL 68 67 GND
220
FFWRT 70 69 EXT_PCLK
10
FSYNC 72 71 SYS_RESET_X
22
UART0_RXD 74 73 UART0_TXD
DTIF_DHEN 76 75 DTIF_DDEN
8
DTIF_DATA(31) 78 77 DTIF_DATA(30)
6 RB1807
GND 80 79 GND
47
4
DTIF_DATA(29) 82 81 DTIF_DATA(28)
2
DTIF_DATA(27) 84 83 DTIF_DATA(26)
DTIF_DATA(25) 86 85 DTIF_DATA(24)
8
DTIF_DATA(23) 88 87 DTIF_DATA(22)
6 RB1808
DTIF_DATA(21) 90 89 DTIF_DATA(20)
47
4
GND 92 91 GND
2
DTIF_DATA(19) 94 93 DTIF_DATA(18)
DTIF_DATA(17) 96 95 DTIF_DATA(16)
8
DTIF_DATA(15) 98 97 DTIF_DATA(14)
6
RB1809
DTIF_DATA(13) 100 99 DTIF_DATA(12)
47
4
DTIF_DATA(11) 102 101 DTIF_DATA(10)
2
GND 104 103 GND
DTIF_DATA(9) 106 105 DTIF_DATA(8)
8
DTIF_DATA(7) 108 107 DTIF_DATA(6)
6 RB1810
DTIF_DATA(5) 110 109 DTIF_DATA(4)
47
4
DTIF_DATA(3) 112 111 DTIF_DATA(2)
2
DTIF_DATA(1) 114 113 DTIF_DATA(0)
GND 116 115 GND
47
DTIF_PLD_EN 118 117 DTIF_PCLK
47
DTIF_PLD_ST 120 119 ENC/DEC_MODE
122 121
GND
9-31 9-31
D E
+3.2V to POST FPGA
DAYTONA-MAIN-GPIO 020
TP1800
+2.5V to POST FPGA
DAYTONA-MAIN-V 020,024
R1811 R1827 0
DAYTONA-MAIN-Fa 020,024
100
22 DAYTONA-MAIN-F
1
DAYTONA-MAIN-C8
3 DAYTONA-MAIN-C6
5 DAYTONA-MAIN-C4
7 DAYTONA-MAIN-C2
1 DAYTONA-MAIN-C0
3
5 DAYTONA-MAIN-Y8
7 DAYTONA-MAIN-Y6
1 DAYTONA-MAIN-Y4
3 DAYTONA-MAIN-Y2
5
DAYTONA-MAIN-Y0
+3.2V to MAP FPGA
7
R1828 0
DAYTONA-MAIN-GPIO_0a 007
+2.5V
220 DAYTONA-MAIN-GPIO_0
FB1812
10uF
FB1804
+1.2V_DAY
FB1805
from DEMUX FPGA
+3.2V
74M-CLK-PLL-DAY-MAIN 017
FB1808
+3.2V
R1818 22
R1830 IC1801 (1/2) R1824
2.2k
NM TC7SZ08FU(TE85R)
47
2
GND 47 R1823
4
R1819 22
1
R1820 22
R1825
47
7 8
RTP-DT30
5 6
RTP-DT28
DAYTONA-MAIN-UART-TX 020
3 4 RTP-DT26
1 2
RTP-DT24
7 8 RTP-DT22
5 6
RTP-DT20
3 4 RTP-DT18
1 2
RTP-DT16
7 8 RTP-DT14
5 6
RTP-DT12
3 4
RTP-DT10
1 2 RTP-DT8
7 8 RTP-DT6
5 6 RTP-DT4
3 4
RTP-DT2
1 2 RTP-DT0
+3.2V
DEC
*: DPR-300 (19/28) of schematic diagram is not described in this manual.
F G
1
+2.5V to ZXCV
DAYTONA-MAIN 020
2
3
005,007,009,011,017
DPR-RESET_2
DAYTONA-MAIN-RESET 020
+3.2V from POST FPGA
+3.2V
IC1801 (2/2)
TC7SZ08FU(TE85R)
VCC
C1807
4
0.1uF
GND
GND
5
DPR-300 (18/28)
BOARD NO. 1-879-649-11
HDCU-300_DPR-300_011_18
H