Sony HXCU-100 Service Manual page 229

from/to DAYTONA MAIN DEC
018 DAYTONA-MAIN-GPIO
018,024 DAYTONA-MAIN-V
018,024 DAYTONA-MAIN-Fa
018 DAYTONA-MAIN-F-RESET
018 DAYTONA-MAIN-UART-RX
018 DAYTONA-MAIN-UART-TX
018 DAYTONA-MAIN-FRSEL
018 DAYTONA-MAIN-FFWRT
018 DAYTONA-MAIN-RESET
015
from DEMUX
017 DEMUX-AUDIO
017 DEMUX-UTIL
017,024
017,024 DEMUX-SKIN-GATE
IC2000 (1/7)
EP1C12F324C8N(300)
4
moni-HD-PB/PR_f6
IO0[D1]
moni-HD-PB/PR_f7 6
IO1/DPCLK1/DQS0L[F1]
7
moni-HD-PB/PR_f4
IO2/LVDS17p[G1]
moni-HD-PB/PR_f5 8
IO3/DQ0L7[H1]
9
moni-HD/SD-Y_f2
IO4/nCSO[J1]
12
SDSDI-YC_f7
IO5/DQ1L0[M1]
13
SDSDI-YC_f5
IO6/LVDS6p[N1]
15
main-HD-F_f
IO7/VREF2B1[R1]
70
moni-HD-PB/PR_f0
IO36/LVDS23n[C2]
71
moni-HD-PB/PR_f2
IO37/LVDS22n[D2]
72
moni-HD-PB/PR_f3
IO38/LVDS21n/DQ0L1[E2]
73
moni-HD-PB/PR_f8
IO39/LVDS19p[F2]
74
moni-HD-PB/PR_f9
IO40/LVDS17n[G2]
75
moni-HD/SD-Y_f1
IO41/LVDS13p[H2]
SDSDI-YC_f2 78
IO42/LVDS10p[L2]
79
SDSDI-YC_f6
IO43/LVDS8n/DQ1L2[M2]
80
SDSDI-H_f
IO44/LVDS6n[N2]
81
main-HD-H_f
IO45/LVDS2p/DQ1L6[P2]
82
main-HD-Y_f1
IO46/LVDS1p[R2]
83
main-HD-Y_f0
IO47/LVDS0p[T2]
moni-HD-PB/PR_f1 129
IO88/LVDS23p/INIT_DONE[C3]
130
moni-HD/SD-Y_f3
IO89/LVDS22p/CLKUSR[D3]
131
moni-HD/SD-Y_f4
IO90/LVDS21p/DQ0L0[E3]
132
moni-HD/SD-Y_f7
IO91/LVDS19n[F3]
133
moni-HD/SD-Y_f6
IO92/LVDS15p[G3]
moni-HD/SD-F_f 134
IO93/LVDS13n[H3]
SDSDI-YC_f0 137
IO94/LVDS10n[L3]
138
SDSDI-YC_f4
IO95/LVDS8p/DQ1L1[M3]
139
SDSDI-YC_f9
IO96/LVDS3p/DQ1L4[N3]
140
main-HD-Y_f2
IO97/LVDS2n/DQ1L7[P3]
141
main-HD-Y_f5
IO98/LVDS1n[R3]
main-HD-Y_f7 142
IO99/LVDS0n[T3]
181
moni-HD/SD-Y_f0
IO137/VREF0B1[D4]
182
moni-HD/SD-Y_f8
IO138/LVDS20p/DQ0L2[E4]
183
moni-HD/SD-Y_f5
IO139/LVDS18p[F4]
184
moni-HD/SD-Y_f9
IO140/LVDS15n/DQ0L4[G4]
185
moni-HD/SD-H_f
IO141/LVDS12p[H4]
187
SDSDI-YC_f1
IO142/PLL1_OUTp[K4]
+3.2V
188
SDSDI-YC_f3
IO143/LVDS9n[L4]
189
SDSDI-YC_f8
IO144/LVDS7n[M4]
190
SDSDI-F_f
IO145/LVDS3n/DQ1L5[N4]
RB2034 191
main-HD-Y_f3
IO146[P4]
S2001 22k
1 2 POST_S1 POST_S1 225
1:CLEAN IO179/LVDS20n/DQ0L3[E5]
226
3 4 POST_S2 POST_S2
2: IO180/LVDS18n[F5]
5 6 227
POST_S3 POST_S3
3: IO181/LVDS14p/DQ0L5[G5]
228
7 8 POST_S4 POST_S4
4: IO182/LVDS12n/DM0L[H5]
230
IO183/PLL1_OUTn[K5]
231
VER_2
GND
IO184/LVDS9p[L5]
232
+3.2V VER_1
IO185/LVDS7p/DQ1L3[M5]
R2049 R2050 R2051 VER_0 233
100k 100k 100k IO186/LVDS4p[N5]
234
main-HD-Y_f4
IO187/DPCLK0/DQS1L[P5]
261
VER_2 IO209/LVDS16p[F6]
262
IO210/LVDS14n/DQ0L6[G6]
VER_1
263
IO211/VREF1B1[H6]
VER_0
265
IO212/ASDO[K6]
266
IO213/LVDS11n[L6]
267
CL2002
IO214/LVDS5p[M6]
1.2
268
R2052 R2053 R2054 IO215/LVDS4n[N6]
100k 100k 100k 269
CL2001
GND
1.2 IO216/LVDS5n[N7]
288
005,022,024,026 R2042 IO234/LVDS16n[F7]
47
293
DPR-RESET_3 IO235/LVDS11p/DM1L[L7]
+3.2V R2005
47 135
005 74M-CLK-FPGA-POST CLK0/LVDSCLK1p[J3]
186
DEMUX-AU-64FS
CLK1/LVDSCLK1n[J4]
R2006
220
HD-F SD-F FRG
TP2001 TP2002 TP2004
R2031 R2032 R2048
100
100 100
022 EXT-CG
HXCU-100
I J
DPR-300 (20/28)
TP2003
TRIAX-H
R2045
100
TRIAX-H
DEMUX-F
RB2022
220
BANK2
3.2V
+1.5V
C2028
L2004 1uF
10uH
L2003
GND
1uH
POST FPGA
C2029 0.1uF
C2003
C2030 0.1uF
10uF GND
6.3V
C2004 1uF
C2020 0.1uF
C2005 1uF
C2021 0.1uF
C2006 1uF
C2022 0.1uF
GND
BANK1
+3.2V
3.2V
L2002 +3.2V-20
1uH
C2002
10uF
6.3V C2007 1uF
C2013 0.1uF
C2014 0.1uF
C2008 1uF
C2015 0.1uF
C2009 1uF
C2016 0.1uF
C2010 1uF
C2017 0.1uF
+2.5V
C2011 1uF
L2001
GND
1uH
C2001 C2012 1uF
10uF
6.3V C2018 0.1uF
C2019 0.1uF
GND
BANK4
2.5V
IC2000 (2/7)
EP1C12F324C8N(300)
to ANALOG FPGA
SYSTEM-HD-F 024
K
DPR-300 (20/28)
+3.2V
R2015
10k
VDD_DAY_CORE_NG/OK 004
IC2000 (3/7)
EP1C12F324C8N(300)
CLK2/LVDSCLK2p[J15]
CLK3/LVDSCLK2n[J16]
IO240/LVDS57n[G12]
IO229/LVDS57p[F12]
IO228/LVDS55n[F13]
IO227/LVDS59n/DQ0R4[G13]
IO226/LVDS63p/DM0R[H13]
IO225/LVDS63n[J13]
IO224/LVDS65p[L13]
IO223/LVDS65n[M13]
IC2000
(4/7)
EP1C12F324C8N(300) IO222/LVDS70n[N13]
IO221/LVDS70p[N12]
IO202/VREF0B3[E14]
IO201/LVDS55p[F14]
IO200/LVDS59p[G14]
IO199/LVDS62n[H14]
IO198/VREF1B3[J14]
IO197[L14]
(6/7) (7/7)
IC2000 IC2000
EP1C12F324C8N(300) EP1C12F324C8N(300) IO196/LVDS67n/DQ1R2[M14]
229 1 IO195/LVDS72p/DQ1R4[N14]
VCCA_PLL1[J5] GND1[A1]
302 3 IO194/LVDS72n/DQ1R5[P14]
VCCA_PLL2[J12] GND2[C1]
16
GND3[T1]
2 18 IO168/LVDS52p[D15]
VCCINT1[B1] GND4[V1]
17 20 IO167/LVDS53p/DQ0R1[E15]
VCCINT2[U1] GND5[V3]
19 33 IO166/LVDS54p/DQ0R3[F15]
VCCINT3[V2] GND6[V16]
34 35 IO165/LVDS58n[G15]
VCCINT4[V17] GND7[V18]
36 37 IO164/LVDS62p[H15]
VCCINT5[U18] GND8[T18]
51 50
VCCINT6[B18] GND9[C18]
53 52 IO163/PLL2_OUTp[K15]
VCCINT7[A17] GND10[A18]
68 54 IO162/LVDS64p[L15]
VCCINT8[A2] GND11[A16] BANK3
313 67 IO161/LVDS67p/DQ1R1[M15]
VCCINT9[L9] GND12[A3]
319 69 3.2V IO160/LVDS69p[N15]
VCCINT10[H10] GND13[B2]
321 84 IO159/DPCLK5/DQS1R[P15]
VCCINT11[J9] GND14[U2]
323 99 IO158/LVDS73n/DQ1R7[R15]
VCCINT12[K10] GND15[U17]
114
GND16[B17]
5 309 IO123/LVDS52n[D16]
VCCIO1_1[E1] GND17[H8]
14 310 IO122/LVDS53n/DQ0R2[E16]
VCCIO1_2[P1] GND18[J8]
289 311 IO121/LVDS54n[F16]
VCCIO1_3[G7] GND19[K8]
294 312 IO120/LVDS58p[G16]
VCCIO1_4[M7] GND20[L8]
56 314 IO119/LVDS61n[H16]
VCCIO2_1[A14] GND21[L10]
65 315
VCCIO2_2[A5] GND22[L11]
254 316 IO118/PLL2_OUTn[K16]
VCCIO2_3[E12] GND23[K11]
257 317 IO117/LVDS64n/DM1R[L16]
VCCIO2_4[E9] GND24[J11]
39 318 IO116/DQ1R0[M16]
VCCIO3_1[P18] GND25[H11]
48 320 IO115/LVDS69n[N16]
VCCIO3_2[E18] GND26[H9]
299 322 IO114/VREF2B3[P16]
VCCIO3_3[M12] GND27[K9]
303 324 IO113/LVDS73p[R16]
VCCIO3_4[H12] GND28[J10]
22 10 IO112/LVDS75n[T16]
GND
VCCIO4_1[V5] GNDA_PLL1[K1]
31 301
VCCIO4_2[V14] GNDA_PLL2[K12]
237 264 IO73/LVDS51n[C17]
VCCIO4_3[P8] GNDG_PLL1[J6]
240 44 IO72/LVDS51p[D17]
VCCIO4_4[P11] GNDG_PLL2[J18]
IO71/DPCLK4/DQS0R[E17]
IO70/LVDS56p[F17]
GND
IO69/LVDS60p/DQ0R5[G17]
IO68/LVDS61p[H17]
IO67/LVDS66p[L17]
IO66/LVDS68p/DQ1R3[M17]
IO65/LVDS71p[N17]
IO64/DQ1R6[P17]
IO63/LVDS74n[R17]
IO62/LVDS75p[T17]
IO25/DQ0R0[D18]
IO24/LVDS56n[F18]
IO23/LVDS60n/DQ0R6[G18]
IO22/DQ0R7[H18]
IO21/LVDS66n[L18]
IO20/LVDS68n[M18]
IO19/LVDS71n[N18]
IO18/LVDS74p[R18]
CL2003
1.2
to Procyon-V
022 PROCYON-RESET
CL2004
1.2
022 ZXCV-MST-HD-F
022 ZXCV-MST-HD-H
022 ZXCV-MST-FRG
022 ZXCV-MST-SD-F
PROCYON MST SYNC
9-33 9-33
L M
27M-CLK-FPGA-POST 005
R2014
47
209
162 R2022 47
CP-CLK_2 005
304
CL2007
1.2
283
CL2005 +3.2V
1.2
282
CL2006
1.2
281 R2020
CL2008
1.2 100k
R2016
280 470
279 R2017 100
to SDI OUT
277
SDI-B-LOCKED 023
276
SDI-B-HD/SD 023 to MB
275 R2018 100
REAR-SEL-B-HD/SD_out 002
274 R2019 100
REAR-SEL-A-HD/SD_out 002
SDI-DIAG_NG/OK 002,004
252 MA1
-12V-CHARGE-PUMP 002
251
SDI-A-LOCKED 023
250
SDI-A-HD/SD 023
249
SDI-OUT-RESET 023
248 SDI-B-C7
246
SDI-B-C4
245
SDI-A-C0
244 SDI-A-C1
243
SDI-A-C2
214
MA3
213 CPU-A0_f
212
SDI-B-Y9
211
SDI-B-Y5
210 SDI-B-Y0
208 SDI-B-C6
1 2
CPU-D0_f CPU-D0
207
SDI-B-C3
RB2024
CPU-D1_f 3 4 CPU-D1
206 SDI-A-Y5
220
CPU-D2_f 5 6 CPU-D2
205 SDI-A-C3
CPU-D3_f 7 8 CPU-D3
204
SDI-A-C6
CPU-D4_f 1 2 CPU-D4
203 SDI-A-C5
RB2025
3 4
CPU-D5_f CPU-D5
220
CPU-D6_f 5 6 CPU-D6
167 CPU-A1_f
7 8
CPU-D7_f CPU-D7
166
CPU-RD_f
CPU-A0_f 7 8 CPU-A0
165
SDI-B-Y8
CPU-A1_f 5 6 RB2026 CPU-A1
164 SDI-B-Y3
220
CPU-RD_f 3 4 CPU-RD
163
SDI-B-C8
CPU-WR_f 1 2 CPU-WR
220
CPU-CS4_f R2021 CS_POST
161
SDI-B-C5
005,007,011,017,022,024,025
160 SDI-B-C0
CPU_I/F
159
SDI-A-Y6
158
SDI-A-Y3
157 SDI-A-Y0
156
SDI-A-C8
155 SDI-A-C4
113 CPU-WR_f
112
CPU-CS4_f CONFIG_DATA0
111
CL2009 CONFIG_DCLK
1.2
110 SDI-B-Y6
109
SDI-B-Y2 CONFIG_nCE_2-3
108 SDI-B-C9 CONFIG_nCE_3-4
105
SDI-B-C1 CONFIG_nCONFIG
104 SDI-A-Y8 CONFIG_nSTATUS
103
SDI-A-Y4 CONFIG_CONF_DONE
102
SDI-A-Y1
101 SDI-A-C9
007,017,024
100
SDI-A-C7
CONFIG_CHAIN
49
CL2010
1.2
47
SDI-B-Y7
1 2
46 SDI-B-Y4
45 IC700 IC1700
SDI-B-Y1
42 SDI-B-C2
MAP DEMUX
41 EPCS16
SDI-A-Y9
EP1C20 EP1C20
40 SDI-A-Y7
38
SDI-A-Y2
EPR2
to SDI OUT
SDI-A_out 023
SDI-B_out 023
from/to MB(SY)
RCP-PWR-NG-STATUS_if 002
SY_UT 002
to ANALOG FPGA
ANALOG 024
*: DPR-300 (19/28) of schematic diagram is not described in this manual.
N O
1
AUDIO SRAM
IC2002
IDT71V016SA15PHG-TL
+3.2V +3.2V
C2023 C2024
0.1uF 0.1uF
RB2027 11 33
GND GND
220
18 VDD1 VDD2 38
MA15 1 2
A15 I/O15
3 4 19 37
MA14
A14 I/O14
20 36
MA13 5 6
A13 I/O13
21 35
MA12 7 8
A12 I/O12
MA11 1 2 24 32
A11 I/O11
RB2028
25 31
MA10 3 4
A10 I/O10
220
MA9 5 6 26 30
A9 I/O9
27 29 RB2032
MA8 7 8
A8 I/O8 220
1 2 42 16 8 7
MA7 MD7
A7 I/O7
RB2029 43 15
MA6 3 4 6 5 MD6
220 A6 I/O6
44 14
MA5 5 6 4 3 MD5
A5 I/O5
MA4 7 8 1 13 2 1 MD4
A4 I/O4 2
2 10
MA3 1 2 8 7 MD3
A3 I/O3
RB2030
3 4 3 9 6 5
MA2 MD2
220 A2 I/O2
4 8
MA1 5 6 4 3 MD1
A1 I/O1
7 8 5 7 2 1
MA0 MD0
A0 I/O0
RB2033
7 8 6
MCE
CS 220
0.5mA MOE 5 6 41
OE
17 22
MWE 3 4
WE NC1
1 2 40 23
BHE NC2
39 28
RB2031 BLE NC3
VSS1 VSS2
47
12 34
GND GND
3
+3.2V-20
IC2000 (5/7)
EP1C12F324C8N(300)
R2023
R2047
10k 10k
107
TDI[J17]
247
TMS[K14]
43
TCK[K18]
R2025
278
0 TDO[K13]
NM 290
DATA0[H7]
11
DCLK[L1]
R2024
1k
291
nCE[J7]
77
nCEO[K2]
76
nCONFIG[J2]
300
nSTATUS[L12]
4
106
CONF_DONE[K17]
+3.2V-20
136
MSEL0[K3]
292
MSEL1[K7]
GND
3 4
IC2000 IC2400
POST ANALOG
EP1C12 EP1C12
5
DPR-300 (20/28)
BOARD NO. 1-879-649-11
HDCU-300_DPR-300_011_20
P