Table of Contents
Advertisement
UX-22oocMu/cMC
MT215tXNfJCMc
[2] Circuit description
of control PWB
1. General description
Fig. 2 shows the functional
blocks of the control PWB, which is com-
posed of 5 blocks.
2) M27C4001
(IC18, IC19): pin-32 DIP (ROM)
EPROM of 2Mbit equipped
with software for the main CPU.
3) SRM2B257SLMX70
(IC17, IC24): pin-28 SOP (RAM)
Line memory for the main CPU system RAM area and coding/decoding
process. Used as the transmission
buffer.
Memory of recorded data such as daily report and auto dials. When the
power is turned off, this memory is backed up by the lithium battery.
4) MS1111514800 (IC16, IC23): pin-28 SOJ (RAM)
Image memory for recording process.
l
Memory for recording pixel data at without paper.
Fig. 2 Control PWB functional
block diagram
2. Description of each block
(1) Main control block
The main control block is composed of HITACHI CPU (SH2),
ROMX2 (256KByte)
RAMXP (32KByte),
DRAMXP (512KByte).
Devices are connected
to the bus to control the whole unit.
1) SH7040 (IC12)
:
pin-112 QFP (SH7040)
The CPU Integrated Facsimile Controllers.
SH7040(SH2),
contains an internal 32 bit microprocessor
with an exter-
nal 16 bit address space and dedicated circuitry optimized for facsimile
image processing and facsimile machine control and monitoring.
g
II
#
Fig. 3
'
5-2
Advertisement
Table of Contents
