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Table 6.
RGMII Interface Signal Descriptions (Sheet 1 of 2)
Signal Name
TXC_0
TXC_1
TXC_2
TXC_3
TD3_0
TD2_0
TD1_0
TD0_0
TD3_1
TD2_1
TD1_1
TD0_1
TD3_2
TD2_2
TD1_2
TD0_2
TD3_3
TD2_3
TD1_3
TD0_3
TX_CTL_0
TX_CTL_1
TX_CTL_2
TX_CTL_3
RXC_0
RXC_1
RXC_2
RXC_3
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Type
Standard
Designator
AA1
AD7
2.5 V
Output
AC20
CMOS
AB14
AA3
Y3
Y2
Y1
AD9
AB9
AB7
AC7
2.5 V
Output
CMOS
AB23
AB22
AB21
AB20
V17
V16
V15
V14
AB2
Y8
2.5 V
Output
AC22
CMOS
V12
V4
AD11
2.5 V
Input
AA24
CMOS
V23
Description
Source Synchronous Transmit Clock.
This clock is supplied synchronous to the transmit
data bus in either RGMII or GMII mode.
Transmit Data.
Bits [3:0] are clocked on the rising edge of TXC.
Bits [7:4] are clocked on the falling edge of TXC.
NOTE: Shares data signals TXD[3:0]_n with the
GMII interface.
Transmit Control.
TX_CTL is TX_EN on the rising edge of TXC and a
logical derivative of TX_EN and TX_ER on the
falling edge of TXC.
NOTE: TX_CTL multiplexes with TX_EN_n on the
GMII interface.
Receiver Reference Clock.
Operates at:
125 MHz for 1 Gigabit
25 MHz for 100 Mbps
2.5 MHz for 10 Mbps
NOTE: Shares the same balls as RXC on the
GMII interface.
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