Intel IXF1104 Datasheet page 11

4-port gigabit ethernet media access controller
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126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)........................................................ 199
127 RX FIFO Padding and CRC Strip Enable ($0x5B3) ................................................................. 200
128 RX FIFO Transfer Threshold Port 0 ($0x5B8) .......................................................................... 201
129 RX FIFO Transfer Threshold Port 1 ($0x5B9) .......................................................................... 201
130 RX FIFO Transfer Threshold Port 2 ($0x5BA).......................................................................... 202
131 RX FIFO Transfer Threshold Port 3 ($0x5BB).......................................................................... 202
132 TX FIFO High Watermark Ports 0 - 3 ($0x600 - 0x603) .......................................................... 203
133 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A - 0x60D)............................................ 204
134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 - 0x617) .............................................205
135 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E).............................................. 206
137 TX FIFO Port Reset ($0x620)................................................................................................... 207
138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 - 0x624) .................................... 208
139 TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 - 0x629) ......................................209
140 TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D - 0x630)............................................... 210
141 TX FIFO Port Drop Enable ($0x63D)........................................................................................210
142 MDIO Single Command ($0x680)............................................................................................. 211
143 MDIO Single Read and Write Data ($0x681)............................................................................211
144 Autoscan PHY Address Enable ($0x682)................................................................................. 212
145 MDIO Control ($0x683).............................................................................................................212
146 SPI3 Transmit and Global Configuration ($0x700) ................................................................... 213
147 SPI3 Receive Configuration ($0x701) ...................................................................................... 215
148 Address Parity Error Packet Drop Counter ($0x70A) ............................................................... 219
149 TX Driver Power Level Ports 0 - 3 ($0x784) ............................................................................. 220
150 TX and RX Power-Down ($0x787) ........................................................................................... 220
151 RX Signal Detect Level Ports 0 - 3 ($0x793) ............................................................................220
152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) .............................................. 221
153 Optical Module Status Ports 0-3 ($0x799)................................................................................ 222
154 Optical Module Control Ports 0 - 3 ($0x79A) ............................................................................222
2
155 I
C Control Ports 0 - 3 ($0x79B) ...............................................................................................223
2
156 I
C Data Ports 0 - 3 ($0x79F) ................................................................................................... 223
157 Product Information ..................................................................................................................230
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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